• Journal of Positioning, Navigation, and Timing
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• 제4권1호
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• pp.17-23
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• 2015

With the increase in the risk of GPS jamming, the development and application of anti-jamming GPS techniques have been actively performed. As the objective performance verification of developed techniques is important, equipment development for verification and discussion on anti-jamming performance test method and procedure have also been conducted. However, most tests are related to the specification of equipment and therefore detailed procedure of the performance verification of an anti-jamming system needs to be developed. In this study, requirements for anti-jamming performance verification were described, and test configurations and performance evaluation items depending on three kinds of test methods (lab test, basic outdoor test, and chamber test) were suggested for anti-jamming performance verification.

• Structural Engineering and Mechanics
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• 제65권2호
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• pp.203-211
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• 2018

This paper introduces the development process of NCC(New Concrete Cutting) system and analyzes first verification test. Based on the first verification test results, some problems of NCC system have been newly modified. We carry out the second verification test. We tried to verify cutting performance and dust control efficiency of NCC system through the cutting test of concrete bridge piers. In particular, this verification test strives to solve the problem of concrete dust, which is the biggest problem of dry cutting method. The remaining dust problems in cutting section tried to solve through this verification test. This verification test of the NCC system shows that the dust problem of dry cutting method is closely controlled and solved. In conclusion, the proposed NCC method is superior to the dry cutting method in all aspects, including cutting performance, dust vacuum efficiency and cooling effect. The proposed NCC system is believed to be able to provide eco-friendly cutting technology to various industries, such as the removal of the SOC structures and the dismantling of nuclear plants, which have recently become a hot issue in the field of concrete cutting.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 하계학술대회 논문집 B
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• pp.842-844
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• 2004

The Back Up Breaker and Making Switch are very important equipments for the short circuit test facility, and contacts are the most important parts of the above switches. There are very many kind of contacts according to switches characteristic and should be done the verification test before use, especially development contacts. This study describes the class of switches, arc chute, material of whole contacts and essential test for verification. The essential test for verification are dielectric test, mechanical operation test, short-time withstand current test, load current breaking test, and short-circuit making current test etc.

• 제어로봇시스템학회논문지
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• 제14권8호
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• pp.824-836
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• 2008

Relaxed static stability(RSS) concept has been applied to improve aerodynamic performance of modern version supersonic jet fighter aircraft. Therefore, flight control systems are necessary to stabilize an unstable aircraft, and provides adequate handling qualities and achieve performance enhancements. Standard FCSDVP (Flight Control System Design and Verification Process) is provided to reduce development period of the flight control system. In addition, if this process is employed in developing flight control system, it reduces the trial and error for development and verification of flight control system. This paper addresses the flight control system design and verification process for the RSS aircraft utilizing design goal based on military specifications, linear and nonlinear system design and verification based on universal software, handling quality test based on HILS(Hardware In-the-Loop Simulator) environment, and ground and flight test results to verify aircraft dynamic flight responses.

• 항공우주기술
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• 제11권1호
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• pp.158-168
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• 2012

본 논문에서는 나로호 2단 킥모터 TVC 노즐에 대한 행정확인시험 방법과 행정확인시험 데이터로부터 TVC 운용 특성을 분석하는 과정 및 결과에 대해 다루었다. 개루프 행정확인 시험을 통해 TVC 스트로크와 포텐셔미터 전압 간의 관계를 분석하고, 폐루프 행정확인시험을 통해 노즐정렬오차, TVC 구동오차, TVC 중립위치, 플렉스씰 노즐의 회전중심위치, 비행시험후 분석에 사용할 노즐각 환산계수 등을 분석할 수 있음을 보였다. 아울러, 나로호 1호기 및 2호기 TVC 시스템에 대해 행정확인시험을 수행한 결과 TVC 운용 관련 모든 파라미터가 정상 범위 내에서 설정되었음을 정량적인 수치로써 제시하였다.

• 한국항행학회논문지
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• 제27권6호
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• pp.782-787
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• 2023

KASS (korea augmentation satellite system) 시스템 통합 및 검증(IVQ; integration, verification, qualification) 활동은 시스템 및 하위시스템 요구사항 검증 활동으로 IART(inspection, analysis, review of design, test) 기반으로 상세설계 (CDR; critical design review) 이후 하위시스템 공장수락시험 (FAT; factory acceptance test)부터 현장수락시험 (SAT; site acceptance test) 그리고 시스템 통합 검증 시험 (TRR; test readiness review) 까지 수행하였다. FAT 단계의 활동은 개발된 장비를 테스트 플랫폼에 설치하고 각 장비별 인터페이스 검증과 통합운영국(KCS; kass control station)과의 연동시험을 통해 성능을 검증하였다. SAT 단계의 활동은 FAT 단계에서 검증된 KRS (kass reference station), KPS (kass processing station), KUS (kass uplink station), KCS를 운영 현장에 설치하고 검증하는 단계이며 개발 일정 및 여건을 고려하여 3단계로 구분하여 수행하였다. TRR 단계의 활동은 항공위성1호기에서 방송되는 SBAS (satellite based augmentation system) 메시지를 이용하여 SAT을 통해 검증된 장비를 FAT 단계에 수행했던 시험 항목과 추가 시험 항목 검증을 통해 전체 시스템에 대한 성능 검증을 완료하였다.

• 대한전자공학회논문지SD
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• 제43권7호
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• pp.38-49
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• 2006

본 논문에서는 SoC를 검증 및 테스트하기 위한 새로운 개념의 칩을 제안하고 이를 SwToC(System with Test on a Chip)라 명명한다. SwToC는 SoC의 임베디드 프로세서에 재구성 가능한 로직을 추가하여 칩의 물리적인 결함을 테스트할 수 있을 뿐만 아니라 기존의 기법으로는 수행이 어려웠던 테스트 단계에서의 디자인 검증이 가능하도록 한 칩을 말한다. 제안한 개념의 칩은 고속 검증이 가능하며 테스트를 위해 많은 비용이 소모되는 ATE 가 불필요한 장점을 갖고 있다. 제안한 칩의 디자인 검증 및 테스트 기능을 평가하기 위하여 임베디드 프로세서가 내장된 상용 FPGA를 이용하여 SwToC를 구현하였으며, 구현 결과 제안한 칩의 실현 가능성을 확인하였고 적은 비용의 단말기를 통한 테스트가 가능함은 물론 기존의 검증기법에 비해 고속 검증이 가능함을 확인하였다.

• ETRI Journal
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• 제11권4호
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• pp.22-36
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• 1989

In this paper, a design and implementation of an efficient protocol verification system named LOVE has been described. The LOVE has been developed specifically for LOTOS. It performs not only protocol syntax validation (PSV) but also protocol functional verification(PFV). The PSV is a test to check if a protocol is free from protocol syntax errors such as deadlocks and livelocks. The PFV confirms whether or not a protocol achieves its functional objectives. For the PSV, the reachability analysis is employed, and the observational equivalence test is used for the PFV. For protocol verification using the LOVE, a schematic protocol verification methodology has been outlined.

• 한국철도학회논문집
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• 제7권2호
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• pp.114-119
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• 2004

According to the computerization of railway signalling systems. the communication protocol for interface between these systems are required. Therefore the new communication protocol for railway signaling system is required. Generally, there are two verification method for new designed protocol in the industrial and academic fields. One is the laboratory testing method which is very popular and general technique. In our research the comparison between existing and new designed protocol for signaling is described and the verification test results are also represented. From these laboratory test, we are verified the conformance of new designed protocol. Another method is verified by formal method. The format verification method is widely used at safety-critical system design but this approach is nor popular at verification communication protocol. However it is very important to verify the safety of new designed protocol for railway signaling system because signaling systems are very safety-critical systems. So, the methodology for formal verification of designed protocol is also reviews in this paper.

• 반도체디스플레이기술학회지
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• 제23권1호
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• pp.25-35
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• 2024

In the present modern day, as the complexity and size of SoC(System on Chip) increase, the importance of design verification are increasing, Therefore it takes a lot of time to verify the design. There is an emerging need to manage the verification environment faster and more efficiently by reusing the existing verification environment. UVM-based verification is a standardized and highly reliable verification method widely adopted and used in the semiconductor industry. This paper presents a UVM-based verification for the 4 tap equalizer module with a systolic array structure. Through the constraints randomization, it was confirmed that various test scenarios stimulus were generated. In addition, by verifying a simulation comparing the actual DUT outputs with the MATLAB reference outputs, the reuse and efficiency of the UVM test bench could be confirmed.