• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.20 no.7
• /
• pp.1342-1354
• /
• 2016

As Internet, and hardware technology are in rapid process, using rate and penetration rate of Internet of Things are increasing. Internet of Things is the physical objects with network which embedded with electronics, software, sensors, and network. Smart Home-kit to operate refrigerators, washing machines, light bulbs, and such internet of things by a smartphone has been realized. However, it is difficult to use a good quality of software based on IoT. It is because that the study related to quality evaluation of software based on IoT is deficient compared with increase amount of IoT devices. Software based on IoT includes mobility, transportability, real time accessibility and hardware characteristics. Therefore, it is necessary to have differentiated quality standards and quality model. Software quality evaluation model for IoT is proposed to satisfy these needs. Evaluation model is mapped by characteristics of IoT software based on ISO/IEC 25000's quality characteristics. Scenario based studies were applied to quality model for verification.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.15 no.1
• /
• pp.14-20
• /
• 2014

This study, the reliability of weapon systems acquisition and research and development in order to increase the effect of the modeling and simulation method has been studied using computational fluid dynamics. Weapon system acquisition, Test & Evaluation for use in the modeling and simulation can reduce the reliability of the time and cost savings and possible predictions and verification, and can provide useful data. However, the current weapon system acquisition and active use of modeling and simulation and verification do not even use the software are restricted. In this study, using computational fluid dynamics (CFD) modeling and simulation using the GAMBIT and FLUENT modeling and simulation was performed. The result is better than previous research results were confirmed in future weapon systems acquisition and research and development are expected to be actively used.

• Proceedings of the Korean Information Science Society Conference
• /
• 2004.10c
• /
• pp.511-513
• /
• 2004

위성의 부분체 또는 탑재컴퓨터 및 탑재소프트웨어에 대한 검증시험을 수행하기 위해서는 위성개발에 사용하며 그 기능이 검증된 상용프로그램을 사용하는 것이 일반적이다. 그러나 위성 영령의 전송 및 텔레메트리 데이터의 전송과 분석을 위한 프로그램은 위성에 사용되는 종류 및 포맷에 따라 다양한 형태로 수정되어야 하기 때문에 자체 제작한 프로그램을 사용하게 된다. 99년에 발사되어 성공적으로 임무를 수행하고 있는 다목적실용위성 1호 및 현재 개발이 진행 중인 다목적실용위성 2호의 개발과정에서는 LEX와 YACC이라는 구문분석기를 이용한 VTSP(Verification Test Script Parser) 프로그램이 탑재소프트웨어의 검증시험에 사용되었다. VT5P는 실시간 데이터 전송 및 분석이 가능하지만 UNIX 환경에서만 실행되므로 윈도우 환경에서 작업하던 일반 사용자들에게는 익숙하지 않은 시험환경을 제공하여 텍스트 기반의 작업이 필요하므로 시험 수행에 여러 어려움들이 발생한다. 이러한 단점들을 보완하기 위하여 윈도우 기반의 검증시험 프로그램인 SATS(Spacecraft Automatic Test Script)를 개발하였다. 본 논문에서는 대부분의 사용자들에게 익숙한 윈도우 환경을 제공하며 이더넷을 통하여 장소에 상관없이 다중의 개발자가 시험을 수행할 수 있는 SATS의 개발현황과 수행환경에 대하며 소개한다.

• The Journal of the Korea Contents Association
• /
• v.8 no.7
• /
• pp.75-84
• /
• 2008

Concurrency and synchronization problems are often caused by database applications concurrently accessing databases managed by DBMS. Most commercial DBMSs support isolation levels to resolve these problems. Verification of isolation levels are most important because consistency and integrity constraints of the database can be violated according to isolation levels of transactions that consists of database applications. We propose a test tool set to verify and reveal faulty settings of isolation levels and implement a prototype of the test tool set. The proposed tool set analyzes the SQL statements of ESQL/C programs, attaches the test codes to verify isolation levels, runs the test transactions and detects errors.

• Proceedings of the KIEE Conference
• /
• 2006.10c
• /
• pp.139-141
• /
• 2006

Quantum-dot Cellular Automata (QCA) is one of the most promising next generation nano-electronic devices which will inherit the throne of CMOS which is the domineering implementation technology of large scale low power digital systems. In late 1990s, the basic operations of the QCA cell were already demonstrated on a hardware implementation. Also, design tools and simulators were developed. Nevertheless, its design technology is not quite ready for ultra large scale designs. This paper proposes a new approach which enables the QCA designs to inherit the verification methodologies and tools of CMOS designs, as well. First, a set of disciplinary rules strictly restrict the cell arrangement not to deviate from the predefined structures but to guarantee the deterministic digital behaviors. After the gate and interconnect structures of the QCA design are identified, the signal integrity requirements including the input path balancing of majority gates, and the prevention of the noise amplification are checked. And then the digital logic is extracted and stored in the OpenAccess common engineering database which provides a connection to a large pool of CMOS design verification tools. Towards validating the proposed approach, we designed a 2-bit QCA adder. The digital logic is extracted, translated into the Verilog net list, and then simulated using a commercial software.

• KIPS Transactions on Software and Data Engineering
• /
• v.4 no.2
• /
• pp.71-76
• /
• 2015

In similarity join processing, a general technique employs a generation-verification framework, which includes two phases: the first phase generates a set of candidate pairs from a collection of records; and the second phase verifies each candidate pair by computing real similarity. In order to reduce the number of candidate pairs in the verification phase, the median of one record of each candidate pair is used as a filter in this paper to test whether the other record can has the proper number of overlapped tokens. We propose a similarity join algorithm with the median filter, and show that the proposed algorithm has better performance in execution time than recent algorithms without the filter through extensive experiments on real-world datasets.

• Transactions of the Korean Society of Mechanical Engineers A
• /
• v.41 no.5
• /
• pp.367-374
• /
• 2017

The goal of this study was to develop control algorithms to improve the steering performance of a 120-ton all-terrain crane. To accomplish this, a hydraulic steering system for the crane was modeled using AMESim software, and a PID steering control algorithm was designed in the MATLAB/Simulink environment. The performance of the designed controller was verified through multiphysics co-simulations based on a real-time simulator.

• Journal of the Korean Society for Precision Engineering
• /
• v.19 no.7
• /
• pp.97-105
• /
• 2002

The use of rapid prototyping (RP) has reduced time to market, cut total costs and improved product quality by giving design and manufacturing teams the opportunity to verify and fine tune designs before committing them to expensive tooling and fabrication. In order to improve their unique characteristics according to the working principles, Variable Lamination Manufacturing process (VLM-ST) and corresponding CAD/CAM software (VLM-Slicer) is developed. The objective of this study is to improve the accuracy of VLM-ST process, and it can be done by offset fur cutting error correction, cutting path overrun fur sharp edge and reference shape generation for off-line stacking. It has been shown that, through the verification experiments for given practical shapes, the proposed algorithms are effective for diverse categories of three-dimensional shapes.

• Proceedings of the Korean Information Science Society Conference
• /
• 2006.06a
• /
• pp.226-228
• /
• 2006

In this paper we describe a simulation and development framework for designing mobile 3D graphics architectures. We are developing a simple and flexible simulation and verification environment (SVE) that uses gITrace's ability to intercept and redirect an OpenGL/ES streams. In combination wlth gITrace to trace OpenGL/ES commands, the SVE simulates the behavior of mobile 3D graphics pipeline during playback of traces, and then produces the second geometry trace that can be used as a test vector for the Verilog/HDL RT-level model. By comparing the frame-by-frame results, we can conduct architectural verification. To demonstrate the functionality of the SVE, we show the implementation of the verified mobile 3D architecture on a FPGA board. For this, we also present an application development environment (ADE) includes a mobile graphics API and a device driver interface (DDI). The proposed two software environments, the SVE and the ADE could be used fer developing and testing mobile applications, architectural study and speculative hardware designs.

• The Journal of the Korea Contents Association
• /
• v.8 no.5
• /
• pp.61-71
• /
• 2008

It is often claimed that the descriptive way of documentation is insufficient to define software requirements as being unambiguous. This is caused by not only the difference of knowledge and understanding of the stakeholder as to system but also the difference in the way of documentation like method of representation as well as depth of description. The study explains the process and results of applying a diagraming tool like UML to improve the requirements of GLORY(GLObal Resource management sYstem) initially defined in descriptive way. Especially, the result shows that the requirements are more accurately improved with the good hierarchies and well-leveled functionalities, with the help of diagraming tool, expecting easy maintenance of requirements and prevention of omission of requirements.