• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.10
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• pp.46-52
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• 2009

A Multi-Core/Multi-Thread architecture is adopted for the Shader processor to enhance the processing performance. The Shader processor is designed to utilize its processing core IP for multiple purposes, such as Vertex-Shading, Rasterization, Pixel-Shading, etc. In this paper, we propose a 'Rasterization based on Vector Algorithm' that makes parallel pixels processing possible with Multi-Core and Multi-Thread architecture on the Shader Core. The proposed algorithm takes only 2% operation counts of the Scan-Line Algorithm and processes pixels independently.

• IEMEK Journal of Embedded Systems and Applications
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• v.8 no.2
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• pp.87-93
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• 2013

In this paper, we implemented and evaluated the performance of a vector-based rasterization algorithm of 3D graphics using a SIMD-based many-core processor that consists of 4,096 processing elements. In addition, we compared the performance and efficiency of the rasterization algorithm using the many-core processor and commercial GPU (Graphics Processing Unit) system which consists of 7 GPUs and each of which have 512 cores. Experimental results showed that the SIMD-based many-core processor outperforms the commercial GPU system in terms of execution time (3.13x speedup), energy efficiency (17.5x better), and area efficiency (13.3x better). These results demonstrate that the SIMD-based many-core processor has potential as an embedded mobile processor.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.1
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• pp.17-24
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• 2014

In this paper, we implement and evaluate the performance of a vector-based rasterization algorithm for 3D graphics by using a SIMD (single instruction multiple data) many-core processor architecture. In addition, we evaluate the impact of a data-per-processing elements (DPE) ratio that is defined as the amount of data directly mapped to each processing element (PE) within many-core in terms of performance, energy efficiency, and area efficiency. For the experiment, we utilize seven different PE configurations by varying the DPE ratio (or the number PEs), which are implemented in the same 130 nm CMOS technology with a 500 MHz clock frequency. Experimental results indicate that the optimal PE configuration is achieved as the DPE ratio is in the range from 16,384 to 256 (or the number of PEs is in the range from 16 and 1,024), which meets the requirements of mobile devices in terms of the optimal performance and efficiency.

• Journal of the Korean Institute of Landscape Architecture
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• v.27 no.4
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• pp.137-142
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• 1999

The purpose of this study is to develope a CAD-based tool for rasterization of polygonal vector map in AutoCAD. To identity the layer property of polygonal entity with user-defined coordinates as topology, algorithm in processing entity data of selection set that intersected with scan line was used, and the layers were extracted sequentially by sorted intersecting points in data-list. In addition to the functions for querying and modifying topology, two options for mapping were set up to construct plan projection type and to change meshes' properties in existing DTM data. In case of plan projection type, user-defined cell size of 3DFACE mesh is available for more detailed edge, and topological draping on landform can be executed in case of referring DTM data as an AutoCAD's drawing. The concept of algorithm was simple and clear, but some unexpectable errors were found in detecting intersected coordinates that were AutoCAD's error, not the utility's. Also, the routines to check these errors were included in algorithmic processing. Developed utility named MESHMAP was written in entity data control functions of AutoLISP language and dialog control language(DCL) for the purpose of user-oriented interactive usage. MESHMAP was proved to be more effective in data handling and time comparing with GRIDMAP module in LANDCADD which has similar function.