• ETRI Journal
• /
• v.27 no.5
• /
• pp.635-638
• /
• 2005

Spatial audio coding (SAC) is an extremely high compact representation of encoded multi-channel audio material. This paper suggests a multi-channel audio service in the terrestrial digital multimedia broadcasting (T-DMB) system using a novel SAC tool, which is called a virtual source location information (VSLI)-based SAC tool. Intensive experiments are presented to evaluate the validity of the proposed VSLI-based SAC tool, and prototypical systems are also presented to demonstrate the reliability of the proposed multi-channel T-DMB system in real applications.

• ETRI Journal
• /
• v.28 no.2
• /
• pp.219-222
• /
• 2006

Virtual source location information (VSLI) has been newly utilized as a spatial cue for compact representation of multichannel audio. This information is represented as the azimuth of the virtual source vector. The superiority of VSLI is confirmed by comparison of the spectral distances, average bit rates, and subjective assessment with a conventional cue.

• Journal of Broadcast Engineering
• /
• v.10 no.3
• /
• pp.328-338
• /
• 2005

Technology for compressing low-bitrate multichannel audio coding is being standardized owing to the increasing need of consumer for multichannel audio contents. In this paper we propose the sound source location cue coding (SSLCC) for extremely compressing multichannel audio to be suitable at the narrow bandwidth transmission environment. To improve the compression capability of the conventional binaural cue coding(BCC), the SSLCC adopts the virtual source location information (VSLI) as a spatial cue parameter, a symmetric uniform quantizer, and Huffman coder. The objective and subjective assessment results show that the SSLCC provides lower bitrate and better audio quality than conventional BCC method.

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.419-420
• /
• 2000

This paper describes the innovation of VLSI design methodology in the coming decade. Technology trend of VLSI fabrication is surveyed first. Then the so-called “design crisis” is analyzed. Finally, possible design methodology to overcome the design crisis is discussed.

• Journal of the Institute of Electronics Engineers of Korea SP
• /
• v.47 no.5
• /
• pp.18-24
• /
• 2010

In this paper, a new matrix decoding system using vector based Virtual Source Location Information (VSLI) is proposed as an alternative to the conventional Dolby Pro logic II/IIx system for reconstructing multi-channel output signals from matrix encoded two channel signals, Lt/Rt. This new matrix decoding system is composed of passive decoding part and active part. The passive part makes crude multi-channel signals using linear combination of the two encoded signals(Lt/Rt) and the active part enhances each channel regarding to the virtual source which is emergent in each inter channel. Since the virtual sources are related to the perceptual sound images in virtual sound field, the reconstructed multi-channel sound results in good dynamic perception and stable image localization. Moreover, the good channel separation is maintained with nonlinear trigonometric enhancing function.

• Proceedings of the IEEK Conference
• /
• 2001.09a
• /
• pp.245-248
• /
• 2001

본 논문에서는 연집 오류(burst error)에 우수한 정정 능력을 보이는 고속 RS(Reed-Solomon) 복호기를 제안한다. 제안된 RS 복호기는 RS(n, k, t); (37 < n ≤ 255, 21 < k ≤ 239, t = 8)의 사양을 지원하며 수정 유클리드 알고리즘(modified Euclid´s algorithm)을 이용한 시스톨릭 어레이(systolic array) 방식의 병렬처리 구조로 설계되었다. 고속 RS 복호기의 효율적인 VSLI 설계를 위하여 새로운 방식의 수정 유클리드 알고리즘 연간 회로를 제안한다. 제안된 수정 유클리드 알고리즘 회로는 2t + 1의 연산 지연 시간을 갖으며 기존 구조의 연산 지연 시간인 3t + 37에 비하여 t = 8 인 경우 약 72%의 연산 지연이 감소하였다. 제안된 구조를 VHDL을 이용하여 설계하였으며 SAMSUNG 0.5㎛(KG80) 라이브러리를 이용하여 논리 합성과 타이밍 검증을 수행하였다. 합성된 RS 복호기의 총 게이트 수는 약 77,000 개이며 최대 80MHz의 동작 속도를 나타내었다.

• IEIE Transactions on Smart Processing and Computing
• /
• v.5 no.5
• /
• pp.349-357
• /
• 2016

The era of the Internet of Things (IoT) is upon us. In this era, minimizing power consumption becomes a primary concern for system-on-chip designers. While traditional power minimization and dynamic power management (DPM) techniques have been heavily explored to improve the power efficiency of devices inside very large-scale integration (VLSI) platforms, there is one critical factor that is often overlooked, which is the power conversion efficiency of a power delivery network (PDN). This paper is a tutorial that focuses on the power conversion efficiency of the PDN, and introduces novel methods to improve it. Circuit-, architecture-, and system-level approaches are presented to optimize PDN designs, while case studies for three different VSLI platforms validate the efficacy of the introduced approaches.

• ETRI Journal
• /
• v.29 no.1
• /
• pp.99-102
• /
• 2007

The channel level difference (CLD) is a main parameter in the reference model 0 (RM0) for MPEG Surround. Nevertheless, the CLD quantization method in the RM0 has problems such as the lack of theoretical background and inappropriate quantization levels. In this letter, a new CLD quantization method is proposed based on the virtual source location information which has strength in the quantization process. From experimental results, it is confirmed that the proposed scheme greatly reduces the quantization distortions measured in dB and degrees without any additional complexity.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.25 no.4B
• /
• pp.708-714
• /
• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• The Transactions of the Korea Information Processing Society
• /
• v.4 no.2
• /
• pp.628-638
• /
• 1997

This paper describes an implementation of fault simulator that can switch level fault models such as transistor stuck-open and stuck-closed faults as well as stuck-at faults. It overcomes the limitation when only stuck-at faults are used in VLSI circuits. Signal flow of a transistor switch is bidirectional in its nature, but most of signal flows in a switch level circuits, about 95%, are in one direction. This fault simulator focuses on the way which changes a switch level circuit into a graph model with two directed edges. Two paths from Vdd to ground and from ground to directions. Logic simulation is performed along dominant signal flows. The switch level fault simulation estimates the dominant path by injecting switch-level fualts, and pattern vectors are used for faults simulation. Experimental results are shown to demonstrate correctness of the fault simulator.