• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.583-585
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• 2004

VLSI가 고성능화 됨에 따라 CAD 툴 또한 그에 맞게 발전 및 이용되고 있다. 하지만 이러한 CAD 툴들은 Synopsys, ModelSim과 같이 고가의 라이센스 정책을 가지고 있기 때문에, 대부분 워킹 그룹 또는 연구 그룹 단위로 관리 및 사용되고 있다. 특정 그룹에서 효율적인 CAD 툴의 관리 및 사용을 위해서는 CAㅇ 툴의 설치, 라이센스의 설정, 서버 및 사용할 클라이언트 환경 설정 등 않은 부분을 사랑이 직접 구축해야 한다. 본 논문에서는 Jini 분산 패러다임을 이용하여 CAD 툴 자원을 효율적으로 관리 및 공유할 수 있는 방식을 제안하며, 그 중 씬 클라이언트의 경우 Jini의 Executable 프락시를 이용하여 클라이언트 자원의 설정까지 자동으로 할 수 있는 방법을 제안한다.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.589-591
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• 2004

VLSI 설계 생산성의 향상을 위하여 여러 대학 및 연구소, 기업체들은 다양한 종류의 CAD 툴을 사용하고 있다 각 단체에서 CAD 툴을 사용하기 위해서는 CAD 툴을 설치한 후. 사용자가 직접 라이센스 파일의 위치를 환경변수에 설정하거나, 라이센스 서비스 데몬이 실행되어 있는 컴퓨터의 포트번호와 서버의 이름을 관리자에게 요청하여 환경변수를 직접 설정해주어야 하는 번거로움이 발생한다. 또한, 라이센스의 관리 및 어떤 CAD 툴이 사용 가능한지 확인이 어렵다 본 논문에서는 네트워크 상의 라이센스 서버로부터 vlf요한 라이센스 정보를 찾고, 환경변수를 설정하는 라이센스 처리과정을 보다 효율적으로 하기 위해, 네트워크 상의 서비스 발견과 이용을 쉴게 해주는 Jini를 사용하여 라이센스를 공유하는 방식을 제안한다.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.36C no.1
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• pp.1-11
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• 1999

In this paper, we proposed a design method of parameterized viterbi decoder, which automatically synthsizes the diverse viterbi deciders used in the digital mobile communication systems. It is designed to synthesize a viterbi decoder specified by user-provided parameters. Those parameters are constraint length, code rate generator polynomials of teh convolutional encoder, data rate and bits/frame of the data transmission, and soft decision bits of viterbi decoder. For the design of the parameterized viterbi decoder, we designed a user interface module C-language, and a viterbi decoder module in a hierarchical atructure using VHDL language and its generic statement. For the verification of the parameterized viterbi decoder, we compared our synthesized viterbi decoder with the conventional viterbi decoder which is designed for the IS-95 CDMA system. The proposed design method of the viterbi decoder will be a new method to obtain a required viterbi decoder in a very short time only by supplying the design parameters.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.12
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• pp.41-50
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• 1999

In this paper, the new VLSI architecture of a reconstruction filter for morphological image segmentation is proposed. The filter, based on the $h_{max}$ operation, simplifies the interior of each region while preserving the boundary information. The proposed architecture adopts a partitioned memory structure and an efficient image scanning strategy to reduce the operations. The proposed memory partitioning scheme makes it possible that every data required for processing can be read from each memory at a time, resulting in parallel data processing. By the extended connectivity consideration, the operation is much decreased because more simplification is achieved in scanning stage. The selective raster scan strategy endows the satisfactory noise removal capability with negligible hardware complexity increase. The proposed architecture is designed using VHDL, and functional evaluation is performed by the CAD tool, Mentor. The experiment results show that the proposed architecture can simplify image profile with less than 18% operations of the conventional method.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.3
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• pp.66-76
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• 1995

In this research, a mesh connected VLSI structure is proposed for the real time computation of the generalized Hough transform(GHT). The purpose of the research is to design a generalized Hough transformer that can be realized as a single chip processor. The GHT has been modified to yield a highly parallel structure consisting of simple processing elements(PEs) and communication networks. In the proposed structure, the GHT can be computed by first assigning an image pixel to a PE and performing shift and add operations. The result of the CAD circuit simulation shows that it can be computed in the time proportional to the number of pixels in the pattern. In addition to the Hough transformer, the peak detector has been designed to reduce 1)the number of the I/O operations between the transformer and the host computer and 2) the host computer's burden for peak detection by transmitting only the local peaks detected from the transformed accumulator. It is expected that the proposed single chip Hough transformer with peak detector makes a fast and inexpensive edge based object recognition systems possible for many industrial and military applications.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.8
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• pp.22-38
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• 1997

This paper proposes a new VLSI architecture for morphological filters and presents its chip design and implementation. The proposed architecture can significantly reduce hardware costs compared with existing architecture by using a feedback loop path to reuse partial results and a decoder/encoder pair to detect maximum/minimum values. In addition, the proposed architecture requires one common architecture for both diltion and erosion and fewer number of operations. Moreover, it can be easily extended for larger size morphologica operations. We developed VHDL (VHSIC hardware description language) models, performed logic synthesis using the SYNOPSYS CAD tool. We used the SOG (sea-of-gate) cell library and implemented the actual chip. The total number of gates is only 2,667 and the clock frequency is 30 MHz that meets real-time image processing requirements.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.8
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• pp.514-523
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• 2006

In this paper we propose an extended interleaving technique to improve a detailed placement. The existing row-based interleaving technique allows cells to move only within a row and it can be applied when there is no space between cells. The proposed extended-interleaving technique releases such constraints so that cells can move along with a vertical line parallel to a y-axis and space between cells is properly handled. Converged detailed-placements by a mature CAD tool have been improved by the proposed interleaving technique by 9.5% on average in half-perimeter wire length.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.12
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• pp.680-686
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• 2002

In deep-submicron (BSM) design, coupling effects between wires on the bus cause serious problems such as crosstalk delay, noise, and power consumption. Most of the previous works on bus encoding are targeted either to minimize tile power consumption on bus or to minimize the crosstalk delay, but not both. In this paper, we propose a new bus encoding algorithm that minimizes the power consumption on bus and eliminates the crosstalk delay simultaneously. We formulate and solve the problem by minimizing a weighted sum of the self transition and cross-coupled transition activities on bus From experiments using a set of benchmark designs. it is shown that the proposed encoding technique consumes at least 15% less power over the existing techniques, while completely eliminating the crosstalk delay.

• Journal of Advanced Navigation Technology
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• v.7 no.2
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• pp.206-210
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• 2003

In this paper, we design standard cell libraries using the 0.18um deep submircom CMOS process, and port them into a P&R (Placement and Routing) CAD tool. A simple test chip has been designed in order to verify the functionalities of the 0.18um standard cell libraries whose technical process was provided by Anam semiconductor. Through these experiments, we have found that the new 0.18um CMOS process can be successfully applied to automatic digital system design.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.582-586
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• 1988

This paper describes KUIC_DRC(Kyungpook national University Intelligent CAD_Design Rule Checker) which verifies VLSI layout. It uses modified linked list data structure. The input form is modifed CIF(Caltech Intermediate Form), called KIF(Kyungpook Intermediate Form). It makes error file, a KIF file. It is written in C language and excuted on MS-DOS, in IBM PC/AT.