• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.3
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• pp.220-227
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• 2002

An one-dimensional VLSI array for high speed processing of Fractal image compression was designed. Using again the overlapped input data of adjacent domain blocks in the existing one-dimensional VLSI array, we can save the number of total input for the operations, and so we can save the total computation time. In the design procedure, we considered the data dependences between the input data, reordered the input data to the array, and designed the processing elements. Registers and multiplexors are added for the storing and routing of the input data in some processing elements. Consequently as adding a little hardware, this design shows (N-4B)/4(N-B) times of speed-up compared with the existing array, where N is image size and B is block size.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.4B
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• pp.708-714
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• 2000

In this paper, an one-dimensional VLSI array for high speed processing of fractal image compression algorithm based the quad-tree partitioning method is proposed. First of all, the single assignment code algorithm is derived from the sequential Fisher's algorithm, and then the data dependence graph(DG) is obtained. The two-dimension array is designed by projecting this DG along the optimal direction and the one-dimensional VLSI array is designed by transforming the obtained two-dimensional array. The number of Input/Output pins in the designed one-dimensional array can be reduced and the architecture of process elements(PEs) can he simplified by sharing the input pins of range and domain blocks and internal arithmetic units of PEs. Also, the utilization of PEs can be increased by reusing PEs for operations to the each block-size. For fractal image compression of 512X512gray-scale image, the proposed array can be processed fastly about 67 times more than sequential algorithm. The operations of the proposed one-dimensional VLSI array are verified by the computer simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.5A
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• pp.702-708
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• 2000

In this paper, we designed one-dimensional VLSI array with optimal pipeline period for high speed processing fractal image compression. The algorithm is derived which is suitable for VLSI array from axed block partition algorithm. Also the algorithm satisfies high quality of image and high compression-ratio. The designed VLSI array has optimal pipeline relied because the required processing time of PEs is distributed as same as possible. As this result, we can improve the processing speed up to about 3 times. The number of input/output pins can be reduced by sharing the input/output and arithmetic unit of the domain blocks and the range blocks.

• The Journal of the Acoustical Society of Korea
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• v.12 no.4
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• pp.32-38
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• 1993

2-D FIR 필터를 시스토릭 어레이 구조로 실현하는 방법을 제시하였다. 시스토릭 어레이는 1-D FIR 필터로 부분 실현한 후 병렬연겨랗여 구현하였다. 부분 실현한 시스토릭 어레이의 마지막 입력신호를 다음 단의 입력에 직접연결시킴으로써 입력 지연에 사용되는저장요소를 절약 시킨다. 1-D 시스ㅏ토릭 어레이는 지역통신 접근에 의해 DG를 설계한 후 SFG로으ㅟ 사상을 통해 유도하였다. 유도된 SFG는 DG의 노드가 보다 적은수의 PE에 사상됨으로써 PE의 이용률을 개선할 수 잇다. 유도된 구조는 매우 간단하며, 입력 샘플이 공급되어지면 매 샘플링 기간마다 새로운 출력을 얻는 매우 SHB은 데이터 비율(data rate)을 갖는다. 시스토릭 어레이는 규칙적이고, 모듈성이며, local interconnection, highly synchronized multiprocessing 의 특징을 갖기 때문에 VLSI 실현에 매우 적합하다. PE 셀 구조는 높은 처리율, 최소 계산시간과 최소 파이프라인 주기를 갖도록 설계하였다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.364-370
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• 2002

In this paper, we propose a VLSI array architecture for high speed processing of FBMA. First of all, the sequential FBMA is transformed into a single assignment code by using the index space expansion, and then the dependance graph is obtained from it. The two dimensional VLSI array is derived by projecting the dependance graph along the optimal direction. Since the candidate blocks in the search range are overlapped with columns as well as rows, the processing elements of the VLSI array are designed to reuse the overlapped data. As the results, the number of data inputs is reduced so that the processing performance is improved. The proposed VLSI array has (N$^2$+1)${\times}$(2p+1) processing elements and (N+2p) input ports where N is the block size and p is the maximum search range. The computation time of the rat reference block is (N$^2$+2(p+1)N+6p), and the block pipeline period is (3N+4p-1).

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.265-268
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• 2001

In this paper, we designed one-dimensional VLSI array with high speed processing in Fractal image compression. fractal image compression algorithm partitions the original image into domain blocks and range blocks then compresses data using the self similarity of blocks. The image is partitioned into domain block with 50% overlapping. Domain block is reduced by averaging the original image to size of range block. VLSI array is trying to search the best matching between a range block and a large amount of domain blocks. Adjacent domain blocks are overlapped, so we can improve of each block's processing speed using the reuse of the overlapped data. In our experiment, proposed VLSI array has about 25% speed up by adding the least register, MUX, and DEMUX to the PE.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12A
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• pp.2059-2066
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• 2001

In this paper, we proposed a method to reduce the number of input pins in one-dimensional VLSI array for fractal image compression. We use quad-tree partition scheme and can reduce the number of the input pins up to 50% by sharing the domain\`s and the range\`s data input pins in the proposed VLSI array architecture. Also, we can reduce the input pins and simplify the internal operation circuit of the processing elements by eliminating a few number of bits of the least significant bits of the input data. We simulated using the 256$\times$256 and 512$\times$512 Lena images to verify performance of the proposed method. As the result of simulation, we can decompress the original image with about 32dB(PSNR) in spite of elimination of the least significant 2-bit in the original input data, and additionally reduce the number of input pins up to 25% compared to VLSI array sharing input pins of range and domain.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.38 no.3
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• pp.46-46
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• 2001

본 논문에서는 시스톨릭 어레이에 기반한 모양 적응적 이산 여현 변환(SADCT)의 효율적 VLSI 구조를 제안한다. 모양 적응적 이산 여현 변환은 이산 여현 변환과 달리 변환 크기가 각 블록에서의 객체의 모양에 따라 가변적이므로 기존의 시간 순환구조에서는 각 처리소자의 이용도와 처리속도가 모두 저하된다. 본 논문에서는 이러한 단점을 극복하기 위해 메모리를 필요로 하지 않는 시스톨릭 어레이에 기반한 구조를 제안한다. 제안된 구조에서는 1차원 SADCT를 연속적으로 수행함으로 처리속도를 향상시키고 첫 번째 열의 처리소자들을 마지막 열의 처리소자들과 연결하고, 입력 데이터는 각각의 재배열된 블록에서의 최대 데이터 크기에 따라 각 열에 병렬로 입력하여 처리소자의 이용도를 향상시켰다. 제안된 구조는 VHDL로 기술하고 MentorTM를 이용하여 기능검증을 수행하였다. 검증결과, 하드웨어 복잡도가 다소 증가하나, 처리속도는 기존의 방법에 비해 두 배정도 향상되었다.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.39 no.5
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• pp.34-42
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• 2002

In this paper, we designed the VLSI array architecture for the high speed processing of the motion estimation used by block matching algorithm. We derived the one dimensional systolic array from the full search block matching algorithm. The data and control signals of the proposed systolic array are passed through adjacent processing element. So proposed architecture has temporal and spatial locality. The I/O ports exists only in the first and last processing elements of the array. This architecture has low pin counts and modular expandability. So the proposed array architecture can be cascaded for different block size and search range.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1970-1982
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• 1993

This paper describes an efficient array algorithm for parallel computation of vector-radix two-dimensional (2-D) fast discrete cosine transform (VR-FCT), and its VLSI implementation. By mapping the 2-D VR-FCT onto a 2-D array of processing elements (PEs), the butterfly structure of the VR-FCT can be efficiently importanted with high concurrency and local communication geometry. The proposed array algorithm features architectural modularity, regularity and locality, so that it is very suitable for VLSI realization. Also, no transposition memory is required, which is invitable in the conventional row-column decomposition approach. It has the time complexity of O(N+Nnzp-log2N) for (N*N) 2-D DCT, where Nnzd is the number of non-zero digits in canonic-signed digit(CSD) code, By adopting the CSD arithmetic in circuit desine, the number of addition is reduced by about 30%, as compared to the 2`s complement arithmetic. The computational accuracy analysis for finite wordlength processing is presented. From simulation result, it is estimated that (8*8) 2-D DCT (with Nnzp=4) can be computed in about 0.88 sec at 50 MHz clock frequency, resulting in the throughput rate of about 72 Mega pixels per second.