• Title/Summary/Keyword: VIN

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HPV Detection and Genotyping in Vulvar Squamous Cell Carcinoma in Northern Thailand

  • Siriaunkgul, Sumalee;Settakorn, Jongkolnee;Sukpan, Kornkanok;Srisomboon, Jatupol;Utaipat, Utaiwan;Lekawanvijit, Suree;Khunamornpong, Surapan
    • Asian Pacific Journal of Cancer Prevention
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    • v.15 no.8
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    • pp.3773-3778
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    • 2014
  • Background: The study was aimed to evaluate the prevalence and genotype distribution of HPV infection in vulvar squamous cell carcinoma (SCC) in northern Thailand and the clinicopathological difference with regard to HPV infection status. Materials and Methods: Formalin-fixed paraffin-embedded tissue samples of vulvar SCC diagnosed between January 2006 and December 2012 were collected. HPV infection was detected by nested polymerase chain reaction (PCR) with primers MY09/11 and GP5+/6+. HPV genotyping was performed using the Linear Array Genotyping Test, followed by type-specific PCR targeting the E6/E7 region of HPV16/18/52 if the Linear Array test was negative. The histologic slides of vulvar lesions and the medical records were reviewed. Results: There were 47 cases of vulvar SCC included in the study (mean patient age $57.9{\pm}13.2$ years). HPV infection was detected in 29 cases (62%), all of which had single HPV infections. HPV16 accounted for 23 (49%). The patients with HPV-positive SCC had a significantly younger mean age than those with HPV-negative tumors (52.7 years vs 66.2 years, p<0.001). There was no significant difference in tumor stage distribution with regard to the status of HPV infection. The presence of vulvar intraepithelial neoplasia (VIN) of usual type (basaloid or warty) was significantly more frequent in HPV-positive cases compared with HPV-negative cases (62% vs 6%, p<0.001), whereas differentiated-type VIN was more common in HPV-negative cases (24% vs 0%, p=0.019). Conclusions: HPV infection was detected in 62% of vulvar SCC in northern Thailand. HPV16 was the predominant genotype similar to the data reported from other regions. HPV-positive SCC occurred in younger patients compared with HPV-negative SCC, and was associated with usual-type VIN. Vaccination against HPV16/18 may potentially prevent almost one half of vulvar SCC in northern Thailand.

Integrated illumination Control System Using Digital Adaptation Control (디지털 적응 제어 방식의 조명 제어 시스템의 설계)

  • Song, Moon-Vin;Lee, Seung-Won;Lee, Young-Won;Chung, Yun-Mo
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.732-734
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    • 2004
  • In this paper, it is suggested and implemented that a new structure of illumination control system using the adaptation control method is to control a number of illuminators. IDs is given to each illuminator controller, the systems are connected in serial, and then the main system controls the on and off of the power supply, intensity of illumination, and a failure check.

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Design of Automatic Checking System for Muilt-channel Speakers (다채널 스피커를 위한 자동검사 시스템 설계)

  • Lee, Seung-Won;Song, Moon-Vin;Lee, Tack-Soo;Chung, Yun-Mo
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.843-844
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    • 2006
  • 다채널 스피커를 위한 자동검사 시스템은 아날로그 음향신호를 디지털로 바꾸고 이를 시리얼로 전송한 후 각각의 스피커를 통해서 출력하는 다채널음향 신호의 시리얼 전송기술을 기반으로 한다. 각각의 스피커에는 소형 진동 센서가 장치되어 있어 출력되는 음향신호의 이상 유무를 판별하여 스피커의 방송 상태를 자동으로 검사할 수 있다.

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Hardware Using of the SEED Algorithm (SEED 암호화 알고리즘의 하드웨어 구현)

  • Song, Moon-Vin;Ko, Myung-Kwan;Chung, Yun-Mo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2000.10b
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    • pp.1453-1456
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    • 2000
  • 국내에서는 전자상거래 진흥을 도모하고 정보사회에서의 국가 경쟁력을 확보하기 위해 128비트 블록암호알고리즘인 SEED를 발표하였다. 본 논문에서는 SEED의 하드웨어적인 응용을 위하여 외부 인터페이스를 고려한 고속의 하드웨어 구현에 대하여 연구하였다. VHDL을 이용하여 모델링 하였으며 시뮬레이션 및 합성 과정을 거쳐 수행을 검증하였다.

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Hardware Design of EZW (EZW의 하드웨어 설계)

  • Yi, Doo-Young;Song, Moon-Vin;Lim, Jae-Chung;Sim, Jung-Sub;Chung, Yun-Mo
    • Proceedings of the Korea Information Processing Society Conference
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    • 2003.05a
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    • pp.23-26
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    • 2003
  • 본 논문은 웨이블릿 변환 과정을 통해서 분해한 영상을 Shapiro가 제안한 효율적인 영상 압축 방법인 EZW(Embedded Zerotree Wavelet)알고리즘을 하드웨어로 설계하였다. 이를 위한 하드웨어 구조를 제시하고 VHDL로 모델링 하여 FPGA를 통해 검증하였다.

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