• Journal of the Korea Institute of Information Security & Cryptology
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• v.7 no.1
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• pp.45-56
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• 1997

본 논문에서는, 무선 통신시스템에 적용 가능한 (255,215) BCH부호의 효율적인 복호 알고리즘을 제안하고, 이를 이용하여 5중 에러 정정 부호기 및 복호기를 설계하였다. peterson의 복호기보다 곱셈기, X-or 게이트의 수가 현저히 줄어들었을 뿐만 아니라 역원계산기가 필요 없음이 입증되었고, VHDL을 사용한 컴퓨터 시뮬레이션을 통해서 그 타당성을 검증하였다.

• Journal of Advanced Marine Engineering and Technology
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• v.25 no.2
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• pp.375-382
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• 2001

In this study, an adapted Turbo Coding Algorithm for reducing communication error of a fire detection system for marine vessels, especially image transmission via power lone. Because it is necessary that this system communicate larger and faster than previous method, this study carried out enhancement a decoding speed by adaptation CRC with Turbo Code Algorithm, improvement of metric method, and reduction of decoding delay by using of Center-to-Top method. And the results are as follows: (1) Confirmed that a Turbo Code is so useful methods for reducing communication error in lots of noise environments. (2)Proposed technology in this study speed increasing method of Turbo Coding Algorithm proves 2 times faster than normal Turbo Code and communication error reducing as well in the board made by VHDL software & chips ALTERA company.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.10
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• pp.67-76
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• 1993

This paper presents the design and implementation of SVSIM (Sogang VHDL SIMulator), a multi-level VHDL simulator, designed for the construction of an integrated VGDL design environment. The internal model of SVSIM is the hierarchical C/DFG which is extended from C/DFG to include the network hierarchy and local/glabal control informations. Hierarchical network is not flattened for simulation, resulting in the reduction of space complexity. The predufined/user-defined types except for the record type and the predefined/user-defined attributes are supported in SVSIM. Algorithmic-level descriptions can be siumlated by the support of recursive procedure/function calls. Input stimuli can be generated by command script in stimuli file or in VHDL source code. Experimential results show SVSIM can be efficiently used for the simulation of the pure behavioral descriptions, structural descriptions or mixture of these.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2003.06a
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• pp.300-303
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• 2003

In this paper, a baseband module of the spread spectrum system with FPGA is designed. A spread spectrum system spreads the signal bandwidth necessary for information transmission. We focused on the design of FEC decoder, especially the convolutional code fo constraint length K=3, rate R=l/2, is designed. For the VHDL design the Xilinx Foundation 3.1 is used. As results, a spread spectrum modem with convolutional coding is designed and we have plan to apply this modem to short distances wireless communication.

• The Transactions of the Korea Information Processing Society
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• v.7 no.11
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• pp.3556-3565
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• 2000

가상 프로토타입(Virtual Prototyping: VP) 방법론을 이용하면 내장형 시스템을 설계하고 구현할 때에 비용을 절감하면서 제품의 개발기간을 단축할 수 있다. VP는 S/W component, H/W component 그리고 S/W 와 H/W를 연결하는 Interface component로 구성되어 진다. VP의 구성 요소중 H/W component를 구현하는 방법은 여러 가지가 있었으나 시스템 명세 언어로부터는 하드웨어 컴포넌트로 구현하는 방법을 고려하고자한다. 그러나 시스템 명세 언어로부터 생성된 H/W component 용 VHDL 코드는 항상 합성 가능한 코드라고 할 수 없다. 본 논문에선 시스템 명세 언어로부터 검증을 용이하게 하는 하드웨어 구현을 위하여 명세언어로써 SpecCharts를 이용하고 이로부터 동기적 의미론을 만족하는 합성 가능한 VHDL 코드를 생성하는 방법론을 제시한다.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.425-428
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• 1999

Turbo decoder were shown to achieve performance within 0.7㏈ of the Shannon capacity limit. This constituted a significant gain in power efficiency over other coding techniques known at the time. In this paper, Turbo code with constraint length K＝4, code rate 1/3, frame size 196bits(6 tail bits), 20㎳ frame and 6bit MAP decoder is implemented using VHDL. The designed Turbo code is used for voice service. Interactions of the system are used to attain large performance improvements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.4
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• pp.277-284
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• 2001

Viterbi algorithm is widely used in digital communication system for FEC(forward error correction). Each communication systems based on the Viterbi algorithm use specific Viterbi decoder which has different code parameter values. Even if Viterbi decoder has the same code parameters, it can be varied by the design architecture adopted. We propose the parameterized VHDL model generator for the efficiency of the design. It makes it possible to achieve shorter design time and lower design cost. The model generator searches the design space available and finds out the optimal design point to generate a decoder model.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.3C
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• pp.306-313
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• 2007

In this paper, we efficiently implemented turbo code algorithm in FPGA H/W(hardware) resource. The used turbo code algorithm has the characteristics; the size of constraint is 3, encoder type is 1/3, the size of random interleaver is 2048. The proposed H/W consists of MAP block for calculating alpha and delta using delta value, storing buffer for each value, multiplier for calculating lamda, and lamda buffer. The proposed algorithm and H/W architecture was verified by C++ language and was designed by VHDL. Finally the designed H/W was programmed into FPGA and tested in wireless communication environment for field availability. The target FPGA of the implemented H/W is VERTEX4 XC4VFX12-12-SF363 and it is stably operated in 131.533MHz clock frequency (7.603ns).

• Journal of the Korea Institute of Information Security & Cryptology
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• v.8 no.2
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• pp.93-106
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• 1998

RS부호의 복호 기법은 전체 통신 시스템의 성능 및 복잡도에 큰 영향을 미친다. 지금까지 RS부호의 복호 기법은 다양한 방법에 있으나Euclid알고리즘과 변환복호기법을 이용한 복호 기법은 오류정정능력이 큰 복호 기법으로 널리 적용되고 있다. 본 논문에서는 오류정정능력이 5이상인 RS부호의 복호 알고리즘에 적용될 수 있는 효율적인 복호 알고리즘을 제시하고, 이를 이용하여 5중 오류 정정(31, 21)RS 부호기 및 복호기를 설계하고VHDL을 사용한 컴퓨터 시뮬레션을 통해서 그 타당성을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.185-197
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• 2001

Recently, the design method by VHDL coding and synthesis has been used widely. As the integration ratio increases, the amount design by VHDL at a time also increases so many coding errors occur in a design. Thus, lots of time and effort is dissipated to detect those coding errors. This paper proposed a method to verify the coding errors in VHDL behavioral-level designs. As the methodology, we chose the method to detect the coding error by applying the generated set of verifying patterns and comparing the responses from the error-free case(gold unit) and the real design. Thus, we proposed an algorithm to generate the verifying pattern set for the coding errors. Verifying pattern generation is peformed for each code and the coding errors are classified as two kind: condition errors and assignment errors. To generate the patterns, VHDL design is first converted into the corresponding CDFG(Control & Data Flow Graph) and the necessary information is extracted by searching the paths in CDFG. Path searching method consists of forward searching and backward searching from the site where it is assumed that coding error occurred. The proposed algorithm was implemented with C-language. We have applied the proposed algorithm to several example VHDL behavioral-level designs. From the results, all the patterns for all the considered coding errors in each design could be generated and all the coding errors were detectable. For the time to generate the verifying patterns, all the considered designed took less than 1 ［sec］ of CPU time in Pentium-II 400MHz environments. Consequently, the verification method proposed in this paper is expected to reduce the time and effort to verify the VHDL behavioral-level designs very much.