• Journal of Electrical Engineering and Technology
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• v.9 no.3
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• pp.991-996
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• 2014

Power frequency magnetic field is still a critical problem for new construction of overhead power transmission lines in Korea because most people have been concerned about possibly carcinogenic effects of it. Although reference level of power frequency(60Hz) magnetic field has been set to 200uT in ICNIRP guidelines published in 2010, Korean government has no intention of adjusting 83.3uT specified by law in 2006 to this new reference level in consideration of people's concerns for the time being. Regardless of the current regulated magnetic field value, electric utility company has been trying to reduce magnetic field in the residential area in the vicinity of overhead power transmission lines to take into account of public concerns on the long-term effect of magnetic fields. In an effort to reduce magnetic field, engineering side has made considerable efforts to develop passive loop based, cost-effective mitigation technique of power frequency magnetic field more than ten years. In order to verify developed power frequency magnetic field mitigation technique based on passive loop, a horizontal type of passive loop was designed and installed for commercially operating 154kV overhead power transmission line for the first time in Korea. The measurement results before and after the installation of passive loop showed that magnetic field could be reduced to about 20%. The electrical environmental effects such as AN, RI and TVI were assessed before and after the installation of passive loop and these values were complied with the requirements specified by electric utility. It has been confirmed from the field test results that passive loop could be commercially and cost-effectively utilized to mitigate power frequency magnetic field.

• Journal of the Microelectronics and Packaging Society
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• v.8 no.1
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• pp.19-25
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• 2001

In this paper, the design and simulation results of IF frequency synthesizer section has been described. We has been used 0.8 $\mu\textrm{m}$ BiCMOS device and library of the AMS. IF frequency synthesizer section has been contained IF VCO, Phase Detector, Divide_by_8, Charge Pump and Loop Filter. IF frequency synthesizer has been shown operating voltage of 2.7~3.6 V, control voltage of 0.5~2.7 V and supply current of 11 mA. The measured results have been showed good agreement with the simulation results about supply current.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.91-94
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• 2000

This paper introduces the design of low-power, fast-locking delay locked-loop using complementary pass transistor logic(CPL). Low-power design has become one of the most important in the modem VLSI application. CPL has the advantage of fast speed, high density, and low power with signal buffering between stages. Based on this analysis, we concluded that the I/O performance can be beyond 500㎒, 2-poly, 2-metal 0.65$\mu\textrm{m}$, 3.3V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Advances in Traditional Medicine
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• v.8 no.2
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• pp.171-177
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• 2008

Epigallocatechin 3-gallate (EGCG), one of the major catechins of tea, was isolated from the decaffeinated, crude methanolic extract of Indian green tea (Camellia sinensis L. O. Kuntze) using chromatographic techniques. EGCG was then screened for antidiarrhoeal activity against 30 strains (clinical isolates) of V. cholerae, which is a well known Gram negative bacillus functioning as the pathogen of cholera. V. cholerae strains like V. cholerae 69, 71, 83, 214, 978, 1021, 1315, 1347, 1348, 569B and ATCC 14033 were inhibited by EGCG at a concentration of $25\;{\mu}g/ml$ whereas V. cholerae 10, 522, 976 were even more sensitive, being inhibited at $10\;{\mu}g/ml$ level. However, V. cholerae DN 16, DN 26, 30, 42, 56, 58, 113, 117, 564, 593, 972 and ATCC 14035 were inhibited at $50\;{\mu}g/ml$ level of EGCG. Only four strains were inhibited at $100\;{\mu}g/ml$. In this study the isolated compound was found to be bacteriostatic in its mechanism of action. In the in vivo experiment using the rabbit ileal loop model two different dosages of EGCG ($500\;{\mu}g/ml$ and $1,000\;{\mu}g/ml$) were able to protect the animals when they were challenged with V. cholerae 569B in the ileum.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.27 no.2
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• pp.255-261
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• 2003

It is advantageous to use NDE methods to assess the mechanical properties of materials since the conventional method is time-consuming and sometimes requires cutting of sample from the component. The NDE parameters such as ultrasonic velocity and attenuation, electric resistivity, and magnetic coercive force and remanance have been utilized to evaluate changes of material properties due to heat treatment condition. It has been found that changes of materials properties under quenched and tempered/PWHT treatments could not be detected using EMAT and Electrical resistivity methods. However, victors hardness and magnetic hysteresis loop decreased with heat treatment procedures. These results were obtained using 3Cr-lMo-0.25V steel. The magnetic parameters were found to be most sensitive to changes of material properties.

• ETRI Journal
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• v.30 no.2
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• pp.268-274
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• 2008

This paper proposes an open-loop clock recovery circuit (CRC) using two high-Q dielectric resonator (DR) filters for 39.8 Gb/s and 42.8 Gb/s dual-mode operation. The DR filters are fabricated to obtain high Q-values of approximately 950 at the 40 GHz band and to suppress spurious resonant modes up to 45 GHz. The CRC is implemented in a compact module by integrating the DR filters with other circuits in the CRC. The peak-to-peak and RMS jitter values of the clock signals recovered from 39.8 Gb/s and 42.8 Gb/s pseudo-random binary sequence (PRBS) data with a word length of $2^{31}-1$ are less than 2.0 ps and 0.3 ps, respectively. The peak-to-peak amplitudes of the recovered clocks are quite stable and within the range of 2.5 V to 2.7 V, even when the input data signals vary from 150 mV to 500 mV. Error-free operation of the 40 Gb/s-class optical receiver with the dual-mode CRC is confirmed at both 39.8 Gb/s and 42.8 Gb/s data rates.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.22 no.2
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• pp.85-93
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• 2008

In 22.9[kV]-y distribution systems, underground cables are provided with 3-wire loop multiple-point ground in which each coaxial-neutral line of the distribution cable lines(A, B, C phases) is 3-wire common grounded at every connecting section. In the underground cable distribution systems, circulating current flows in the coaxial-neutral lines and its magnitude amounts to about $40{\sim}50[%]$ load currents, even though loads are balanced. This paper presents a new ground method to overcome such a problem and a comprehensive analysis in tows of current capacity of power cables, induced voltage of cable sheath, and electromagnetic interference voltage from power cable lines.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.8
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• pp.699-705
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• 2008

Capacitance versus voltage (C-V) characteristics of Ge-nanocrystal (NC)-embedded metal-oxide-semiconductor (MOS) capacitors with $HfO_2$ gate material were investigated in this work. The current versus voltage (I-V) curves obtained from Ge-NC-embedded MOS capacitors fabricated with the $NH_3$ annealed $HfO_2$ gate material reveal the reduction of leakage current, compared with those of MOS capacitors fabricated with the $O_2$ annealed $HfO_2$ gate material. The C-V curves of the Ge-NC-embedded MOS capacitor with $HfO_2$ gate material annealed in $NH_3$ ambient exhibit counterclockwise hysteresis loop of about 3.45 V memory window when bias voltage was varied from -10 to + 10 V. The observed hysteresis loop indicates the presence of charge storages in the Ge NCs caused by the Fowler-Nordheim (F-N) tunneling. In addition, capacitance versus time characteristics of Ge-NC-embedded MOS capacitors with $HfO_2$ gate material were analyzed to investigate their retention property.