• Title/Summary/Keyword: V2V communications

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A Study on Thermal Stability Improvement in Ni Germanide/p-Ge using Co interlayer for Ge MOSFETs

  • Shin, Geon-Ho;Kim, Jeyoung;Li, Meng;Lee, Jeongchan;Lee, Ga-Won;Oh, Jungwoo;Lee, Hi-Deok
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.17 no.2
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    • pp.277-282
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    • 2017
  • Nickel germanide (NiGe) is one of the most promising alloy materials for source/drain (S/D) of Ge MOSFETs. However, NiGe has limited thermal stability up to $450^{\circ}C$ which is a challenge for fabrication of Ge MOSFETs. In this paper, a novel method is proposed to improve the thermal stability of NiGe using Co interlayer. As a result, we found that the thermal stability of NiGe was improved from $450^{\circ}C$ to $570^{\circ}C$ by using the proposed Co interlayer. Furthermore, we found that current-voltage (I-V) characteristic was improved a little by using Co/Ni/TiN structure after post-annealing. Therefore, NiGe formed by the proposed Co interlayer that is, Co/Ni/TiN structure, is a promising technology for S/D contact of Ge MOSFETs.

Implementation of Charge-Pump Active-Matrix OLED Panel with $64\;{\times}\;64$ Pixels Using $ITO/SiO_2/ITO$ Capacitors and a-Si:H Schottky Diodes

  • Na, Se-Hwan;Seo, Jong-Wook;Kwak, Mi-Young;Shim, Jae-Hoon
    • 한국정보디스플레이학회:학술대회논문집
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    • 2006.08a
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    • pp.1267-1270
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    • 2006
  • Organic light-emitting diode (OLED) display panel with $64\;{\times}\;64$ pixels utilizing the charge-pump (CP) pixel addressing method was fabricated using conventional thin-film processes. Each pixel consists of a-Si:H Schottky diode and $ITO/SiO_2/ITO$ capacitor. It is shown that CP-OLED is technically feasible for information display and a driving voltage below $4V_{pp}$ is enough for nominal operation.

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Task Scheduling on Cloudlet in Mobile Cloud Computing with Load Balancing

  • Poonam;Suman Sangwan
    • International Journal of Computer Science & Network Security
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    • v.23 no.10
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    • pp.73-80
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    • 2023
  • The recent growth in the use of mobile devices has contributed to increased computing and storage requirements. Cloud computing has been used over the past decade to cater to computational and storage needs over the internet. However, the use of various mobile applications like Augmented Reality (AR), M2M Communications, V2X Communications, and the Internet of Things (IoT) led to the emergence of mobile cloud computing (MCC). All data from mobile devices is offloaded and computed on the cloud, removing all limitations incorporated with mobile devices. However, delays induced by the location of data centers led to the birth of edge computing technologies. In this paper, we discuss one of the edge computing technologies, i.e., cloudlet. Cloudlet brings the cloud close to the end-user leading to reduced delay and response time. An algorithm is proposed for scheduling tasks on cloudlet by considering VM's load. Simulation results indicate that the proposed algorithm provides 12% and 29% improvement over EMACS and QRR while balancing the load.

Implementation of Single-Phase Energy Measurement IC (단상 에너지 측정용 IC 구현)

  • Lee, Youn-Sung;Seo, Hae-Moon;Kim, Dong Ku
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.40 no.12
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    • pp.2503-2510
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    • 2015
  • This paper presents a single-phase energy measurement IC to measure electric power quantities. The entire IC includes two programmable gain amplifiers (PGAs), two ${\sum}{\Delta}$ modulators, a reference circuit, a low-dropout (LDO) regulator, a temperature sensor, a filter unit, a computation engine, a calibration control unit, registers, and an external interface block. The proposed energy measurement IC is fabricated with $0.18-{\mu}m$ CMOS technology and housed in a 32-pin quad-flat no-leads (QFN) package. It operates at a clock speed of 4,096 kHz and consumes 10 mW in 3.3 V supply.

Design of High Speed VRAM ASIC for Image Signal Processing (영상 신호처리를 위한 고속 VRAM ASIC 설계)

  • Seol, Wook;Song, Chang-Young;Kim, Dae-Soon;Kim, Hwan-Yong
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.6
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    • pp.1046-1055
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    • 1994
  • In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

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Analysis of Sensing Mechanisms in a Gold-Decorated SWNT Network DNA Biosensor

  • Ahn, Jinhong;Kim, Seok Hyang;Lim, Jaeheung;Ko, Jung Woo;Park, Chan Hyeong;Park, Young June
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.2
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    • pp.153-162
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    • 2014
  • We show that carbon nanotube sensors with gold particles on the single-walled carbon nanotube (SWNT) network operate as Schottky barrier transistors, in which transistor action occurs primarily by varying the resistance of Au-SWNT junction rather than the channel conductance modulation. Transistor characteristics are calculated for the statistically simplified geometries, and the sensing mechanisms are analyzed by comparing the simulation results of the MOSFET model and Schottky junction model with the experimental data. We demonstrated that the semiconductor MOSFET effect cannot explain the experimental phenomena such as the very low limit of detection (LOD) and the logarithmic dependence of sensitivity to the DNA concentration. By building an asymmetric concentric-electrode model which consists of serially-connected segments of CNTFETs and Schottky diodes, we found that for a proper explanation of the experimental data, the work function shifts should be ~ 0.1 eV for 100 pM DNA concentration and ~ 0.4 eV for $100{\mu}M$.

A Design of High Speed Infrared Optical Data Link IC (고속 적외선 광 송수신 IC 설계)

  • 임신일;조희랑;채용웅;유종선
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.12B
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    • pp.1695-1702
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    • 2001
  • This paper describes a design of CMOS infrared (IR) wireless data link IC which can be used in IrDA(Infrared Data Association) application from 4 Mb/s to 100 Mb/s The implemented chip consists of variable gain transimpedance amplifier which has a gain range from 60 dB to 100 dB, AGC (automatic gain control) circuits, AOC(automatic offset control) loop, 4 PPM (pulse position modulation) modulator/demodulator and DLL(delay locked loops). This infrared optical link If was implemented using commercial 0.25 um 1-poly 5-metal CMOS process. The chip consumes 25 mW at 100 Mb/s with 2.5 V supply voltage excluding buffer amplifier. The die area of prototype IC is 1.5 mm $\times$ 1 mm.

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An Efficient Scheduling Algorithm for 3D-Traffic in OFDMA Systems (OFDMA 시스템에서 3D 트래픽의 효율적 전송을 위한 스케줄링 방안)

  • Kwon, Su-Jin;Chung, Young-Uk;Lee, Hyuk-Joon;Choi, Yong-Hoon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.34 no.10B
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    • pp.1104-1110
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    • 2009
  • 3D A/V services are expected to be a representative service of next generation because it can give more realistic feeling by providing dimensions to the 2D images. In terms of transmission part of 3D A/V systems, however, it is difficult to provide these services on real-time in the wireless OFDMA networks because it has to send large amount of traffic. To address this, we proposed a novel scheduling algorithm which separates a 3D traffic into base layer and enhancement layer, and provides different priority to them. From simulation results, we can show that the proposed algorithm can improve QoS.

Transceiver for Human Body Communication Using Frequency Selective Digital Transmission

  • Hyoung, Chang-Hee;Kang, Sung-Weon;Park, Seong-Ook;Kim, Youn-Tae
    • ETRI Journal
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    • v.34 no.2
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    • pp.216-225
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    • 2012
  • This paper presents a transceiver module for human body communications whereby a spread signal with a group of 64 Walsh codes is directly transferred through a human body at a chip rate of 32 Mcps. Frequency selective digital transmission moves the signal spectrum over 5 MHz without continuous frequency modulation and increases the immunity to induced interference by the processing gain. A simple receiver structure with no additional analog circuitry for the transmitter has been developed and has a sensitivity of 250 ${\mu}V_{pp}$. The high sensitivity of the receiver makes it possible to communicate between mobile devices using a human body as the transmission medium. It enables half-duplex communication of 2 Mbps within an operating range of up to 170 cm between the ultra-mobile PCs held between fingertips of each hand with a packet error rate of lower than $10^{-6}$. The transceiver module consumes 59 mA with a 3.3 V power supply.

An MMIC VCO Design and Fabrication for PCS Applications

  • Kim, Young-Gi;Park, Jin-Ho
    • Journal of Electrical Engineering and information Science
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    • v.2 no.6
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    • pp.202-207
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    • 1997
  • Design and fabrication issues for an L-band GaAs Monolithic Microwave Integrated Circuit(MMIC) Voltage Controlled Oscillator(VCO) as a component of Personal Communications Systems(PCS) Radio Frequency(RF) transceiver are discussed. An ion-implanted GaAs MESFET tailored toward low current and low noise with 0.5mm gate length and 300mm gate width has been used as an active device, while an FET with the drain shorted to the source has been used as the voltage variable capacitor. The principal design was based on a self-biased FET with capacitive feedback. A tuning range of 140MHz and 58MHz has been obtained by 3V change for a 600mm and a 300mm devices, respectively. The oscillator output power was 6.5dBm wth 14mA DC current supply at 3.6V. The phase noise without any buffer or PLL was 93dB/1Hz at 100KHz offset. Harmonic balance analysis was used for the non-linear simulation after a linear simulation. All layout induced parasitics were incorporated into the simulation with EEFET2 non-linear FET model. The fabricated circuits were measured using a coplanar-type probe for bare chips and test jigs with ceramic packages.

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