• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10A
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• pp.1015-1022
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• 2007

In this paper, dual-band digital codec for UHF(Ultra High Frequency) and MW(Micro Wave) is proposed for an RFID reader system. Most RFID systems have been supported only one protocol. But, There are many protocols of each bandwidth. Especially, UHF bandwidth which is widely used on the globe consists of A,B,C type, and more standards will be established. Recently, Since an interest about mobile RFID system is increasing, the RFID system with more than one protocol will be need. Therefore, this paper suggests a dual-band digital codec with UHF and MW bands for an RFID reader system. Standards used in this system are 18000-6C and 18000-4 standards. The digital codec is synthesize by the Quartus II compiler. Target device is EPC20Q240C8 which is family of CycloneII. Main Clock is 19.2MHz and elements of FPGA which is used for the system is 18,752.

• Journal of Digital Contents Society
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• v.16 no.2
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• pp.275-282
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• 2015

Since starting of terrestrial digital broadcasting in 2001, there has been discussion on introduction of multiple broadcasting services, one of advantages of digital broadcasting. In the mean time, task force on terrestrial multiple channel experimental broadcasting was formed with government organizations, broadcasting companies and household appliance companies in Oct. 2013, and terrestrial multiple channel experimental broadcasting was started between Jan. to April, 2014. Based on this experimental result, EBS started 2HD MMS experimental broadcasting first in Korea on Feb. 11, 2015. This study was carried out in consideration of operation of 2 HD channels in existing 6MHz bandwidth based on MPEG-2 codec with development of compression technology. A study on image quality optimization was carried out and applied to 2HD MMS experimental broadcasting through application experiment of variable bit rate and change according to 1080i and 720p scanning type.

• Journal of Korean Society of Archives and Records Management
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• v.24 no.1
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• pp.163-186
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• 2024

With the National Archives of Korea's establishment of the Selection Criteria for Preservation Format of Digital Records (v1.0) in 2022, criteria have been formed to facilitate the selection of appropriate preservation formats for various types of digital records. With the advancement of technology, diverse electronic file types are produced. However, no specific criteria exist for records other than document types, such as PDF/A-1b. Therefore, the purpose of this paper is to derive intrinsic criteria for selecting preservation formats for audiovisual records, particularly focusing on video-type digital records, to expand the scope of the preservation format selection criteria. Initially, significant properties of video-type digital records were determined, forming the basis for the intrinsic criteria. According to these properties, the video types were categorized into container type and codec type, and three and six evaluation criteria items were derived, respectively. By structuring evaluation criteria for each attribute, this paper proposes intrinsic criteria for selecting preservation formats for video-type electronic records.

• Proceedings of the IEEK Conference
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• 2000.06d
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• pp.98-101
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• 2000

On CELP type Vocoders G.723.1 6.3kbps/5.3kbps Dual Rate Speech Codec, which is developed for Internet Phone and videoconferencing, uses VAD(Voice Activity Detection)/CNG (Comfort Noise Generator) in order to reduce the bit rate in a silence period. In order to reduce the bit rate effectively in this paper, we first set the boundary condition of the energy threshold to prevent the consumption of unnecessary processing time, and use three decision rules to detect an active frame by energy, pitch gain and LSP distance. To evaluate the performance of the proposed algorithm we use silence-inserted speech data with 0, 5, 10, 20dB of SNR. As a result when SNR is over 5dB, the bit rate is reduced up to about 40% without speech degradation and the processing time is additionally decreased.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.739-742
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• 1998

실시간 동영상의 전송을 위해 본 논문에서는 USB를 전송매체로 하여 구현했다. USB는 키보드, 스태너, 모뎀등 다양하게 사용되고 있는 인터페이스를 한나로 통일하고, 포트의 부족을 해결하기 위해서 개발된 것으로 고속의 데어터전송(12Mbps)을 가능하다. USB의 고속데이터 전송의 특징은 정지화상(JPEG) 뿐만 아니라 실시간 동영상(MPEG1, MPEG2)의 전송을 가능하게 한다. 본 논문에서는 USB로 실시간 동영상 전송을 위한 시스템 구조를 제시하였고 보다 효율적인 데이터 전송을 위한 USB Data Transfer Type에 관해 연구하였다. 720×480의 동영상의 압축을 위해 기존의 널리 이용되는 DCT대신 wevelet 알고리즘을 이용하였고 실시간 압축과 복원을 위해 video compression codec인 adv601를 사용하여 동영상 및 정지화상압축을 하였다. 또한 DSP(TMS320C32)를 이용하여 Quantization Bin Width Calculation을 함으로써 video bit stream의 크기를 가변적으로 제어하려 하였다. 이로서 동영상의 전송시 발생될 수 있는 데이터 병목현상을 해결 하였고 USB뿐만 아니라 다양한 통신망｛ISDN(128Kbps), T1(1.5Mbps) T3(45Mbps)｝에서의 동영상의 실시간 전송이 가능한 시스템 구조를 제시하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.1
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• pp.35-46
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• 1997

This paper describes a B-ISDN terminal adapter which provides B-ISDN adaptation functions for conventional services such as N-ISDN, video, connectionless data service in the ATM based B-ISDN. These services are provided individually or simultaneously. The B-ISDN terminal adapter offers interfaces of N-ISDN, video codec, Ethernet for supporting conventional services. And it provides various types of services which are available in conventional terminals and networks through B-ISDN. The AAL type 1 is used for N-ISDN and video services, the AAL type 3/4 and 5 are used for LAN service.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.399-402
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• 2004

This paper presents a system-on-chip prototype implementing a full integration for a portable digital audio system. The chip is composed of a audio processor block to implements audio decoding and voice compression or decompression software, a system control block including 8-bit MCU core and Memory Management Unit (MMU) a low power 16-bit ${\Sigma}{\Delta}$ CODEC, two DC-to-BC converter, and a flash memory controller. In order to support other audio algorithms except Mask ROM type's fixed codes, a novel 16-bit fixed-point DSP core with the program-download architecture is proposed. Funker, an efficient power management technique such as task-based clock management is implemented to reduce power consumption for portable application. The proposed chip has been fabricated with a 4 metal 0.25um CMOS technology and the chip area is about 7.1 mm ${\times}$ 7.1mm with 100mW power dissipation at 2.5V power supply.

• Journal of Multimedia Information System
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• v.4 no.4
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• pp.179-188
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• 2017

The Internet Video Coding (IVC) standard is due to be published by Moving Picture Experts Group (MPEG) for various Internet applications such as internet broadcast streaming. IVC aims at three things fundamentally: 1) forming IVC patents under a free of charge license, 2) reaching comparable compression performance to AVC/H.264 constrained Baseline Profile (cBP), and 3) maintaining computational complexity for feasible implementation of real-time encoding and decoding. MPEG experts have worked diligently on the intellectual property rights issues for IVC, and they reported that IVC already achieved the second goal (compression performance) and even showed comparable performance to even AVC/H.264 High Profile (HP). For the complexity issue, however, there has not been thorough analysis on IVC decoder. In this paper, we analyze the IVC decoder in view of the time complexity by evaluating running time. Through the experimental results, IVC is 3.6 times and 3.1 times more complex than AVC/H.264 cBP under constrained set (CS) 1 and CS2, respectively. Compared to AVC/H.264 HP, IVC is 2.8 times and 2.9 times slower in decoding time under CS1 and CS2, respectively. The most critical tool to be improved for lightweight IVC decoder is motion compensation process containing a resolution-adaptive interpolation filtering process.

• ETRI Journal
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• v.22 no.1
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• pp.20-29
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• 2000

In this paper, we present a design of video and audio single chip encoder/decoder for portable multimedia application. The single-chip called as video audio signal processor (VASP) consists of a video signal processing block and an audio single processing block. This chip has mixed hardware/software architecture to combine performance and flexibility. We designed the chip by partitioning between video and audio block. The video signal processing block was designed to implement hardware solution of pixel input/output, full pixel motion estimation, half pixel motion estimation, discrete cosine transform, quantization, run length coding, host interface, and 16 bits RISC type internal controller. The audio signal processing block is implemented with software solution using a 16 bits fixed point DSP. This chip contains 142,300 gates, 22 Kbits FIFO, 107 kbits SRAM, and 556 kbits ROM, and the chip size is $9.02mm{\times}9.06mm$ which is fabricated using 0.5 micron 3-layer metal CMOS technology.