• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권10호
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• pp.546-550
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• 2004

Two fabrication approaches are proposed to planarize the sacrificial layer over hollow structures. One is the photoresist filling method that makes use of photolithography, thermal curing and plasma ashing. The other is the lamination method that is applying pressure and temperature to the organic film over the hollow structures. The fabrication results are compared with those of CMP process. Trenches and cavities with various dimensions have been made for the porposed process. Upon measuring the planarization levels, they are dependent on planarization methods and the geometrical size of hollow structures. The photoresist filling method is so strongly dependent on the width and depth of trenches that we have problems to use it for large dimensional trenches. To the contrary, the flatness of sacrificial layer over the trenches was found to be almost independent of trench dimensions for the lamination method. A CMP process shows the most excellent results, but the fabrication is complicated and the access to it is not so easy. It is important to choose the proper planarization method by considering the required flatness levels, materials to be planarized, and connection between the planarization step and the previous or the following process of it.

• 한국재료학회지
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• 제9권2호
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• pp.124-131
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• 1999

Copper film, which is expected to be used as interconnection material for 1 giga DRAM integrated circuits was deposited on hole and trench patterns by Metal Organic Chemical Vapor Deposition(MOCVD) method. After a reflow process, contact and L/S patterns were filled by copper and the characteristics of the Cu reflow process were investigated. When deposited Cu films were reflowed, grain growth and agglomeration of Cu have occurred in surfaces and inner parts of patterns as well as complete filling in patterns. Also Cu thin oxide layers were formed on the surface of Cu films reflowed in $O_2$ambient. Agglomeration and oxidation of Cu had bad influence on the electrical properties of Cu films especially, therefore, their removal and prevention were studied simultaneously. As a pattern size is decreased, preferential reflow takes place inside the patterns and this makes advantages in filling patterns of deep submicron size completely. With Cu reflow process, we could fill the patterns with the size of deep sub-micron and it is expected that Cu reflow process could meet the conditions of excellent interconnection for 1 giga DRAM device when it is combined with Cu MOCVD and CMP process.

• 한국마이크로전자및패키징학회:학술대회논문집
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• 한국마이크로전자및패키징학회 2003년도 International Symposium
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• pp.261-278
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• 2003

Concepts.Wafer-Level Chip-Scale Concept with Handling Substrate.Low Accuracy Placement Layout with Isolation Trench.Possible Pitch of Interconnections down to $10{\mu}{\textrm}{m}$ (Sn-Grains).Wafer-to-Wafer Equipment Adjustment Accuracy meets this Request of Alignment Accuracy (+/-1.5 ${\mu}{\textrm}{m}$).Adjustment Accuracy of High-Speed Chip-to-Wafer Placement Equipment starts to meet this request.Face-to-Face Modular / SLID with Flipped Device Orientation.interchip Via / SLID with Non-Flipped Orientation SLID Technology Features.Demonstration with Copper / Tin-Alloy (SLID) and W-InterChip Vias (ICV).Combination of reliable processes for advanced concept - Filling of vias with W as standard wafer process sequence.No plug filling on stack level necessary.Simultanious formation of electrical and mechanical connection.No need for underfiller: large area contacts replace underfiller.Cu / Sn SLID layers $\leq$ $10{\mu}{\textrm}{m}$ in total are possible Electrical Results.Measurements of Three Layer Stacks on Daisy Chains with 240 Elements.2.5 Ohms per Chain Element.Contribution of Soldering Metal only in the Range of Milliohms.Soldering Contact Resistance ($0.43\Omega$) dominated by Contact Resistance of Barrier and Seed Layer.Tungsten Pin Contribution in the Range of 1 Ohm

• 한국지반공학회:학술대회논문집
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• 한국지반공학회 1999년도 봄 학술발표회 논문집
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• pp.513-520
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• 1999

20 million tons of coal ash has been produced in Korea annually. This causes the environmental problems and the cost of land for ash pond. However the amount of coal ash for recycling is small because of the low level of recycling technology and the ignorance. As the coal ash has the significant engineering properties, it can be utilized as soft ground stabilizer, backfill materials and so forth. The purpose of this paper is to summarize some of the recycling methods of coal ash. One is structural backfill materials, the other is flowable fill. Optimal mixture ratio(fly ash : bottom ash) is determined for structural backfill materials and the model test is performed. The model test accompanied with physical tests were executed for identifying that the flowable fly ash can be used as fill materials such as trench back filling.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제40회 동계학술대회 초록집
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• pp.68-68
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• 2011

As feature size is smaller, new technology are needed in semiconductor factory such as gap-fill technology for sub 100nm, development of ALD equipment for Cu barrier/seed, oxide trench etcher technology for 25 nm and beyond, development of high throughput Cu CMP equipment for 30nm and development of poly etcher for 25 nm and so on. We are focus on gap-fill technology for sub-30nm. There are many problems, which are leaning, over-hang, void, micro-pore, delaminate, thickness limitation, squeeze-in, squeeze-out and thinning phenomenon in sub-30 nm gap fill. New gap-fill processes, which are viscous oxide-SOD (spin on dielectric), O3-TEOS, NF3 Based HDP and Flowable oxide have been attempting to overcome these problems. Some groups investigated SOD process. Because gap-fill performance of SOD is best and process parameter is simple. Nevertheless these advantages, SOD processes have some problems. First, material cost is high. Second, density of SOD is too low. Therefore annealing and curing process certainly necessary to get hard density film. On the other hand, film density by Flowable oxide process is higher than film density by SOD process. Therefore, we are focus on Flowable oxide. In this work, dielectric film were deposited by PECVD with TSA(Trisilylamine - N(SiH3)3) and NH3. To get flow-ability, the effect of plasma treatment was investigated as function of O2 plasma power. QMS (quadruple mass spectrometry) and FTIR was used to analysis mechanism. Gap-filling performance and flow ability was confirmed by various patterns.

• 한국표면공학회지
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• 제38권1호
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• pp.28-36
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• 2005

In this study, the reflow characteristics of copper thin films which is expected to be used as interconnection materials in the next generation semiconductor devices were investigated. Cu thin films were deposited on the TaN diffusion barrier by metal organic chemical vapor deposition (MOCVD) and annealed at the temperature between 250℃ and 550℃ in various ambient gases. When the Cu thin films were annealed in the hydrogen ambience compared with oxygen ambience, sheet resistance of Cu thin films decreased and the breakdown of TaN diffusion barrier was not occurred and a stable Cu/TaN/Si structure was formed at the annealing temperature of 450℃. In addition, reflow properties of Cu thin films could be enhanced in H₂ ambient. With Cu reflow process, we could fill the trench patterns of 0.16～0.24 11m with aspect ratio of 4.17～6.25 at the annealing temperature of 450℃ in hydrogen ambience. It is expected that Cu reflow process will be applied to fill the deep pattern with ultra fine structure in metallization.

• International Journal of Railway
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• 제7권1호
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• pp.16-23
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• 2014

Reduction in railway-induced vibrations in urban areas is a very challenging task in railway transportation. Many mitigation measures can be considered and applied. Among these, a little attention has been paid to trenches. In this study, a numerical investigation on the effectiveness of in-filled trenches with pipes in reducing railway vibrations due to passing trains is presented. Particularly, a series of two-dimensional dynamic analysis was performed to model the behavior of ballasted railway track under harmonic load with ABAQUS software as a Finite Element method. In so doing, two types of in-filled trenches with pipes with steel and concrete materials have been investigated in this paper. In addition, effectiveness of pipes made of steel and concrete, filled with loose sand and clay in railway-induced vibration reduction has been assessed. The results point out that using in-filled trench with pipes does not effective a lot on railway-induced vibration reduction in comparison to other railway-induced vibration reduction methods. However, in-filled trenches with steel pipes are much more effective than in-filled trenches with concrete pipes. Moreover, filling pipes with loose sand and clay does not have any effect on vibration reduction efficiency of these in-filled trenches.

• 대한토목학회논문집
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• 제11권1호
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• pp.145-151
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• 1991

화력발전소에서 부산되는 석탄회의 매립 성토재로서의 활용이나 폐기된 회사장의 재활용을 위 한 연구의 일환으로, 석탄회의 동적성질을 구명하기 위하여 석탄회를 시료토로하여 진동감쇠비를 구하였으며, 현장(회사장)에서 지반개량 전후 지중벽에 의한 감쇠 특성을 검토한 것이다. 석탄회에 시멘트 12%, 시멘트 9% 또는 약액(물유리), 시멘트 6%를 섞은 공시체 순으로 감쇠비가 크고, 동일 시료의 경우 공극비가 작을수록 감쇠비가 증가하는 것으로 보아 재질의 강성 증대에 따라 감쇠비가 커짐을 알 수 있었다. 회사장에서는 진동전파경로 대책으로 공구를 설치할 경우가 감쇠효과가 가장 크고, 지반을 개량할 경우는 개량지반의 장성이 클수록 감쇠효과가 있다. 이와같이 지반개량을 하게 되면 차수 및 강도증대효과 외에도 진동감쇠효과도 상당히 있는 것으로 판단된다.

• ETRI Journal
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• 제35권3호
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• pp.425-430
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• 2013

In this paper, we propose a triple-gate trench power MOSFET (TGRMOS) that is made through a modified RESURF stepped oxide (RSO) process, that is, the nitride_RSO process. The electrical characteristics of TGRMOSs, such as the blocking voltage ($BV_{DS}$) and on-state current ($I_{D,MAX}$), are strongly dependent on the gate configuration and its bias condition. In the nitride_RSO process, the thick single insulation layer ($SiO_2$) of a conventional RSO power MOSFET is changed to a multilayered insulator ($SiO_2/SiN_x/TEOS$). The inserted $SiN_x$ layer can create the selective etching of the TEOS layer between the gate oxide and poly-Si layers. After additional oxidation and the poly-Si filling processes, the gates are automatically separated into three parts. Moreover, to confirm the variation in the electrical properties of TGRMOSs, such as $BV_{DS}$ and $I_{D,MAX}$, simulation studies are performed on the function of the gate configurations and their bias conditions. $BV_{DS}$ and $I_{D,MAX}$ are controlled from 87 V to 152 V and from 0.14 mA to 0.24 mA at a 15-V gate voltage. This $I_{D,MAX}$ variation indicates the specific on-resistance modulation.