• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2001년도 추계학술대회 논문집
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• pp.181-184
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• 2001

Chemical Mechanical Polishing(CMP) of Shallow Trench Isolation(STI) structure in 0.18 m semiconductor device fabrication is studied. CMP process is applied for the STI structure with and without reverse moat pattern and End Point Detection (EPD) method is tested. To optimize the transistor properties related metal 1 parameters, we studied the correlation between CMP thickness of STI using high selectivity slurry, DOE of gate etch recipe, and 1st metal DC values. Remaining thickness of STI CMP is proportional to the thickness of gate-etch process and this can affect to gate profile. As CMP thickness increased, the N-poly foot is deteriorated, and the P-Poly Noth is getting better. If CD (Critical Dimension) value is fixed at some point, all IDSN/P values are in inverse proportional to CMP thickness by reason of so called Profile Effect. Weve found out this phenomenon in all around DOE conditions of Gate etch process and we also could understand that it would not have any correlation effects between VT and CMP thickness in the range of POE 120 sec conditions. As CMP thickness increased by 100 ${\AA}$, 3.2 u${\AA}$ of IDSN is getting better in base 1 condition. In POE 50% condition, 1.7 u${\AA}$ is improved, and 0.7 u${\AA}$ is improved in step 2 condition. Wed like to set the control target of CD (critical dimension) in gate etch process which can affect Idsat, VT property versus STI topology decided by CMP thickness. We also would like to decide optimized thickness target of STI CMP throughout property comparison between conventional STI CMP with reverse moat process and newly introduced STI CMP using high selectivity slurry. And we studied the process conditions to reduce Gate Profile Skew of which source known as STI topology by evaluation of gate etch recipe versus STI CMP thickness.

• 한국세라믹학회지
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• 제46권1호
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• pp.30-34
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• 2009

A Sand blasting technology has been used to address via and trench processing of glass wafer of optic semiconductor packaging. Manufactured sand blast that is controlled by blast nozzle and servomotor so that 8" wafer processing may be available. 10mm sq test device manufactured by Dry Film Resist (DFR) pattern process on 8" glass wafer of $500{\mu}m's$ thickness. Based on particle pressure and the wafer transfer speed, etch rate, mask erosion, and vertical trench slope have been analyzed. Perfect 500 um tooling has been performed at 0.3 MPa pressure and 100 rpm wafer speed. It is particle pressure that influence in processing depth and the transfer speed did not influence.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 추계학술발표강연 및 논문개요집
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• pp.69-69
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• 2003

최근 trench capacitor, isolation trench, micro-electromechanical system(MEMS), micro-opto-electromechanical system(MOEMS)등의 다양한 기술에 적용될 고종횡비(HAR) 실리콘 식각기술연구가 진행되어 지고 있다. 이는 기존의 습식식각시 발생하는 결정방향에 따른 식각률의 차이에 관한 문제와 standard reactive ion etching(RIE) 에서의 낮은 종횡비와 식각률에 기인한 문제점들을 개선하기 위해 고밀도 플라즈마를 이용한 건식식각 장비를 사용하여 고종횡비(depth/width), 높은 식각률을 가지는 이방성 트랜치 구조를 얻는 것이다. 초기에는 주로 HBr chemistry를 이용한 연구가 진행되었는데 이는 식각률이 낮고 많은양의 식각부산물이 챔버와 시편에 재증착되는 문제가 발생하였다. 또한 SF6 chemistry의 사용을 통해 식각률의 향상은 가져왔지만 화학적 식각에 기인한 local bowing과 같은 이방성 식각의 문제점들로 인해 최근까지 CHF3, C2F6, C4F8, CF4등의 첨가가스를 이용하여 측벽에 Polymer layer의 식각보호막을 형성시켜 이방성 구조를 얻는 multi_step 공정이 일반화 되었다. 이에 본 연구에서는 SF6 chemistry와 소량의 02/HBr의 첨가가스를 이용한 single_step 공정을 통해 공정의 간소화 및 식각 프로파일을 개선하여 최적의 HAR 실리콘 식각공정 조건을 확보하고자 하였다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.178.6-178
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• 2001

Silicon-micromachined microneedle for a biofluid diagnosis system is developed. To fabricate microneedles, two sets of processes are used. One is making buried microchannels in silicon wafer using silicon isotropic etch with a SF6 plasma and then trench-refilling. The other is releasing the body of the microneedle by deep silicon etch. The microneedle has a 4 mm-length and about 12 $\mu\textrm{m}$ diameter buried microchannel, a 1.5 mm$\times$l.5 mm-area reservoir, and about 180 $\mu\textrm{m}$thickness body. Preliminary results indicate that microneedles are capable of flowing fluidic samples. The microneedle with a buried microchannel is expected to be integrated with in vitro diagnosis systems and microfluidic devices.

• Transactions on Electrical and Electronic Materials
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• 제15권1호
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• pp.49-54
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• 2014

In this study, we carried out an investigation of the etch characteristics of silicon (Si) film, and the selectivity of Si to $SiO_2$ in $SF_6/O_2$ plasma. The etch rate of the Si film was decreased on adding $O_2$ gas, and the selectivity of Si to $SiO_2$ was increased, on adding $O_2$ gas to the $SF_6$ plasma. The optical condition of the Si film with this work was 1,350 nm/min, at a gas mixing ratio of $SF_6/O_2$ (=130:30 sccm). At the same time, the etch rate was measured as functions of the various etching parameters. The X-ray photoelectron spectroscopy analysis showed the efficient destruction of oxide bonds by ion bombardment, as well as the accumulation of high volatile reaction products on the etched surface. Field emission auger electron spectroscopy analysis was used to examine the efficiency of the ion-stimulated desorption of the reaction products.

• 전기전자학회논문지
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• 제11권4호
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• pp.235-238
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• 2007

2차원 소자 시뮬레이터인 TMA 메디치를 이용하여 필드링와 깊은 접합 필드링에 대해 연구하였다. 이온 주입될 위치를 미리 트랜치 식각을 시킴으로써 항복전압 특성을 향상시킬 수 있었다. 시뮬레이션 결과 기존 필드링의 항복전압대비 깊은 접합 필드링 항복전압은 약 30%의 증가를 보였다. 깊은 접합 필드링은 같은 면적을 차지하는 조건하에서 설계 및 제작이 비교적 용이하고, 표면 전하의 영향도 적은 것으로 나타났다. 본 논문에서는 여러 분석을 통해 깊은 접합 필드링의 향상된 특성을 논하였다.

• 한국반도체및디스플레이장비학회:학술대회논문집
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• 한국반도체및디스플레이장비학회 2002년도 추계학술대회 발표 논문집
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• pp.14-19
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• 2002

In this study, as Cu diffusion barrier, tantalum nitrides were successfully deposited on Si(100) substrate and SiO2 by plasma assisted atomic layer deposition(PAALD) and thermal ALD, using pentakis (ethylmethlyamino) tantalum (PEMAT) and $NH_3$ as precursors. The TaN films were deposited on $250^{\circ}$C by both method. The growth rates of TaN films were $0.8{\AA}$/cycle for PAALD and $0.75{\AA}$/cycle for thermal ALD. TaN films by PAALD showed good surface morphology and excellent step coverage for the trench with an aspect ratio of h/w - $1.8 : 0.12 \mu\textrm{m}$ but TaN films by thermal ALD showed bad step coverage for the same trench. The density for PAALD TaN was $11g/\textrm{cm}^3$ and one for thermal ALD TaN was $8.3g/\textrm{cm}^3$. TaN films had 3 atomic % carbon impurity and 4 atomic % oxygen impurity for PAALD and 12 atomic % carbon impurity and 9 atomic % oxygen impurity for thermal ALD. The barrier failure for Cu(200nm)/TaN(l0nm)/$SiO_2(85nm)$/Si structure was shown at temperature above $700^{\circ}$C by XRD, Cu etch pit analysis.

• 대한전자공학회논문지
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• 제24권1호
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• pp.91-96
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• 1987

Plasma etching can obtain less damaged etch surface than reactive ion etching. This study was performed to get anisotropic etching characteristics of Si using two step etching technique with C2CIF5 and SF6 gas mixture. The results show that the etch rate and aspect ratio of silicon was increased with increment of SF6 contents. The bulging phenomenon on trench side wall in the plasma one-step etching technique was eliminated by the two step etching technique. The anisotropy was decreased from 12(at 120m Torr) to 2.2(at 400m Torr) with increasing the chamber pressure. At the low rf power (350 watts) anisotrpy of silicon was obtained 7 lower than that of high rf power (650 watts. A:~9). In Summary we obtained anisotropic etching profiles of silicon with e 6\ulcornerm depth by using the plasma two-step etching technique.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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• pp.61.1-61.1
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• 2015

Nanoscale semiconductor plasma processing has become one of the most challenging issues due to the limits of physicochemical fabrication routes with its inherent complexity. The mission of future and emerging plasma processing for development of next generation semiconductor processing is to achieve the ideal nanostructures without abnormal profiles and damages, such as 3D NAND cell array with ultra-high aspect ratio, cylinder capacitors, shallow trench isolation, and 3D logic devices. In spite of significant contributions of research frontiers, these processes are still unveiled due to their inherent complexity of physicochemical behaviors, and gaps in academic research prevent their predictable simulation. To overcome these issues, a Korean plasma consortium began in 2009 with the principal aim to develop a realistic and ultrafast 3D topography simulator of semiconductor plasma processing coupled with zero-D bulk plasma models. In this work, aspects of this computational tool are introduced. The simulator was composed of a multiple 3D level-set based moving algorithm, zero-D bulk plasma module including pulsed plasma processing, a 3D ballistic transport module, and a surface reaction module. The main rate coefficients in bulk and surface reaction models were extracted by molecular simulations or fitting experimental data from several diagnostic tools in an inductively coupled fluorocarbon plasma system. Furthermore, it is well known that realistic ballistic transport is a simulation bottleneck due to the brute-force computation required. In this work, effective parallel computing using graphics processing units was applied to improve the computational performance drastically, so that computer-aided design of these processes is possible due to drastically reduced computational time. Finally, it is demonstrated that 3D feature profile simulations coupled with bulk plasma models can lead to better understanding of abnormal behaviors, such as necking, bowing, etch stops and twisting during high aspect ratio contact hole etch.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2007년도 춘계학술발표회 초록집
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• pp.151-152
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• 2007

최근들어 Device 크기가 100nm 이하로 줄어듦에 따라 High Density Plasma Chemical Vapor Deposition(HDP-CVD) 기술로는 100nm 이하의 gap에 Aspect ratio가 6:1 이상 되는 STI(Shallow Trench Isolation) 구조를 Void 없이 채우는 것이 불가능해 지고 있다. 이를 극복하기 위하여 여러 방면으로 연구가 수행되어지고 있다. 그 방법 중의 하나인 Dep/Etch/Dep Cycle이 이번 연구에서 사용되었으며, 일반적인 HDP CVD보다 더 낮은 압력에서 증착과 식각이 수행되었다. 그 결과 다른 여러 방법들보다 좋은 막질을 얻을 수 있었으며, Gap fill 성능을 향상 시킬 수 있었다.