• Title/Summary/Keyword: Trench Edge Termination

Search Result 6, Processing Time 0.019 seconds

A Study of SiC Trench Schottky Diode with Tilt-Implantation for Edge Termination (Edge Termination을 위해 Tilt-Implantation을 이용한 SiC Trench Schottky Diode에 대한 연구)

  • Song, Gil-Yong;Kim, Kwang-Soo
    • Journal of IKEEE
    • /
    • v.18 no.2
    • /
    • pp.214-219
    • /
    • 2014
  • In this paper, the usage of tilt-implanted trench Schottky diode(TITSD) based on silicon carbide is proposed. A tilt-implanted trench termination technique modified for SiC is proposed as a method to keep all the potentials confined in the trench insulator when reverse blocking mode is operated. With the side wall doping concentration of $1{\times}10^{19}cm^{-3}$ nitrogen, the termination area of the TITSD is reduced without any sacrifice in breakdown voltage while potential is confined within insulator. When the trench depth is set to 11um and the width is optimized, a breakdown voltage of 2750V is obtained and termination area is 38.7% smaller than that of other devices which use guard rings for the same breakdown voltage. A Sentaurus device simulator is used to analyze the characteristics of the TITSD. The performance of the TITSD is compared to the conventional trench Schottky diode.

Design of Main Body and Edge Termination of 100 V Class Super-junction Trench MOSFET

  • Lho, Young Hwan
    • Journal of IKEEE
    • /
    • v.22 no.3
    • /
    • pp.565-569
    • /
    • 2018
  • For the conventional power MOSFET (metal-oxide semiconductor field-effect transistor) device structure, there exists a tradeoff relationship between specific on-state resistance (Ron,sp) and breakdown voltage (BV). In order to overcome this tradeoff, a super-junction (SJ) trench MOSFET (TMOSFET) structure with uniform or non-uniform doping concentration, which decreases linearly in the vertical direction from the N drift region at the bottom to the channel at the top, for an optimal design is suggested in this paper. The on-state resistance of $0.96m{\Omega}-cm2$ at the SJ TMOSFET is much less than that at the conventional power MOSFET under the same breakdown voltage of 100V. A design methodology for the edge termination is proposed to achieve the same breakdown voltage and on-state resistance as the main body of the super-junction TMOSFET by using of the SILVACO TCAD 2D device simulator, Atlas.

The Research on Trench Etched Field Ring with Dual Ion-Implantation for Power Devices (이중 이온주입 공정을 이용한 트렌치 필드링 설계 최적화 및 전기적 특성에 관한 연구)

  • Yang, Sung-Min;Oh, Ju-Hyun;Bae, Young-Seok;Sung, Man-Young
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.23 no.5
    • /
    • pp.364-367
    • /
    • 2010
  • The dual ion-implantation trench edge termination techniques were investigated and optimized using a two-dimensional device simulator. By trenching the field ring site which would be dual implanted, a better blocking capability can be obtained. The results show that the p-n junction with dual implanted junction field-ring can accomplish nearly 20% increase of breakdown voltage in comparison with the conventional trench field-rings. The fabrication is relatively difficult. But the trench etched field ring with dual ion-implantation is surpassed for breakdown voltage and consume same area and extensive device simulations as well as qualitative analysis confirm these conclusions.

The Research of Deep Junction Field Ring using Trench Etch Process for Power Device Edge Termination

  • Kim, Yo-Han;Kang, Ey-Goo;Sung, Man-Young
    • Journal of IKEEE
    • /
    • v.11 no.4
    • /
    • pp.235-238
    • /
    • 2007
  • The planar edge termination techniques of field-ring and deep junction field-ring were investigated and optimized using a two-dimensional device simulator TMA MEDICI. By trenching the field ring site which would be implanted, a better blocking capability can be obtained. The results show that the p-n junction with deep junction field-ring can accomplish near 30% increase of breakdown voltage in comparison with the conventional field-rings. The deep junctionfield-rings are easy to design and fabricate and consume same area but they are relatively sensitive to surface charge. Extensive device simulations as well as qualitative analyses confirm these conclusions.

  • PDF

Design of Unified Trench Gate Power MOSFET for Low on Resistance and Chip Efficiency (낮은 온저항과 칩 효율화를 위한 Unified Trench Gate Power MOSFET의 설계에 관한 연구)

  • Kang, Ey-Goo
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
    • /
    • v.26 no.10
    • /
    • pp.713-719
    • /
    • 2013
  • Power MOSFET operate voltage-driven devices, design to control the large power switching device for power supply, converter, motor control, etc. We have optimal designed planar and trench gate power MOSFET for high breakdown voltage and low on resistance. When we have designed $6,580{\mu}m{\times}5,680{\mu}m$ of chip size and 20 A current, on resistance of trench gate power MOSFET was low than planar gate power MOSFET. The on state voltage of trench gate power MOSFET was improved from 4.35 V to 3.7 V. At the same time, we have designed unified field limit ring for trench gate power MOFET. It is Junction Termination Edge type. As a result, we have obtained chip shrink effect and low on resistance because conventional field limit ring was convert to unify.

Variation of Electrical Properties with Edge Termination in Mesh Type Trench Double Diffused MOSFETs (TDMOS) for High Power Application

  • Na, Gyeong-Il;Kim, Sang-Gi;Gu, Jin-Geun;Yang, Il-Seok;Lee, Jin-Ho;Kim, Jong-Dae
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2011.02a
    • /
    • pp.110-110
    • /
    • 2011
  • 현재 전력 반도체는 신재생/대체 에너지 시스템, 자동차/전기자동차, 디스플레이/LED 드라이브 IC 등과 같이 산업용뿐만 아니라 가정용에서도 그 수요가 급증하고 있다. 이러한 전력 반도체는 각 시스템에서 전력 변환, 분배 및 관리를 하는 역할을 하게 되는데, 이러한 전력 시스템에 적용되기 위해서는 고속 스위칭, 낮은 전력 손실 및 발열, 소형화 등의 특성이 요구되어진다. 이러한 특성을 만족하기 위해 현재 전력반도체는 수평형 소자에서 수직 형태로의 구조적 변경을 꽤하고 있으며, 또한 수직형 구조에서도 더욱 소형화와 고밀도 전류, 낮은 전력 손실 특성을 구현하기 위해 여러 가지 형태의 어레이 기술을 개발하고 있다. 본 연구에서는 사각 형태의 어레이 (square array, mesh type)를 가지는 수직형 TDMOS (Trench double diffused metal oxide effect transistor)에서 트렌치 부분을 중심으로 액티브 영역과 그 외각 영역의 도핑 농도와 접합 깊이의 변화에 따른 전기적 특성 변화를 파악함으로써 TDMOS의 안정적인 구동 영역을 확보하기 위한 연구를 수행하였다. 본 연구는 silvaco 시뮬레이션 툴을 이용하여 실제 소자 제작 공정과 유사한 형태로의 공정을 가상적으로 진행하고, 액티브 영역과 그 외각 영역의 도핑 및 접합 깊이를 결정하는 이온 주입량과, 후속 열처리의 온도와 시간 등을 변화함으로써 그 전기적 특성을 상호 비교하였다.

  • PDF