• Journal of Korea Technical Association of The Pulp and Paper Industry
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• v.42 no.1
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• pp.26-34
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• 2010

Effects of drying condition (IR radiation) on the optical properties and the printability of coated paper were elucidated at various latex sizes and low and high coating color concentrations. It was found that the smaller latex provided better rheology and higher dry and wet pick strength than the larger one. The high solids coating resulted in higher paper gloss and smaller roughness than the low solids coating, even though the clay addition was reduced by 20 parts in the high solids coating. Increasing IR radiation prohibited binder migration into the base paper. Thus it improved binder distribution and decreased pores in the coated layer, resulting in the increased dry and wet pick strength and the improved printing gloss. On the other hand, the color trapping and ink set-off was impaired with increasing IR radiation. Print mottle index passed through a maximum with increasing IR radiation.

• Korean Journal of Microbiology
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• v.22 no.1
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• pp.19-28
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• 1984

The nematode-trapping process by Arthrobotrys conoides was investigated with the aid of scanning and transmission electron microscopy. 1. A. conoides captures nematode by means of three-dimensional network. 2. The wall of trap cell was thicker than that of vegetative hypha and the trap cell was more rich in cell organelles such as endoplasmic reticulum, mitochondria and electrondense granule. 3. The electron-dense granule, which could be found only in trap organs, gradually disappeared during its penetration into nematode cuticle. 4. The osmiophilic area was found at adhering site between the trap organ and nematode cuticle. 5. In some cases, any appressorium was not found at the site of penetration. 6. When the fungal-nematode culture was conserved for 2~3 weeks, numerous young nematodes were found to be adhered to spores, resulting in death.

• Journal of Korean Society for Atmospheric Environment
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• v.16 no.4
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• pp.381-388
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• 2000

Ceramic foam prepared with cordierite as a starting material by foam method was tested to evaluate the feasibility as a filter for the dust collection in hot gas. Two different types of agents Benzethonium chloride (BZTC, C27H42NO2Cl) and Sodium Lauryl Sulfate(SLS, CH3(CH2)11OSO3Na) were used as foaming agents in foaming process. Porosityof ceramic foam was about 80% and mean pore size were 100${\mu}{\textrm}{m}$ for SLS agent and 200 ${\mu}{\textrm}{m}$ for BZTC. It was observed that ceramic foam was composed of continuous macro-pore structure with opening windows interconnecting macro-pores. The surface of ceramic foam support of was coated with cordierite particles ranged from 20${\mu}{\textrm}{m}$ to 50${\mu}{\textrm}{m}$ Meso-pore size in the coating layer on ceramic foam was below 10${\mu}{\textrm}{m}$. While air permeability of the support increased with increasing macro-pore size coated ceramic filters showed a constant permeability without regard to the macro-pore size of the support. The permeabuilities of support varied in the range of 600$\times$10-13m2 to 1000$\times$10-13m2. For the case of coated ceramic filter it was about 200$\times$10-13m2. As a result of particle trapping test by using fly ash the particle removal efficiency was over the 99.9%.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.13 no.6
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• pp.279-283
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• 2003

In this study, ZnTe : S single crystal thin films substituted by sulfur were grown on GaAs (100) substrates by hot-wall epitaxy. The photoluminescence (PL) characteristics of ZnTe : S single crystal thin films was measured to investigate the effects due to sulfur atoms in the ZnTe layer. The Peak of 2.339 eV identified as the isoelectronic center was observed in low temperature PL spectrum, but PL spectra which the origin had not been well-explained were not observed. Temperature dependence of PL intensities of the light hole free exciton was explained by extrinsic self-trapping. Besides it is reported that the emission lines near absorption edge at room temperature were observed.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.2
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• pp.113-119
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• 2005

4H-SiC planar MESFETs were fabricated using ion-implantation on semi-insulating substrate without recess gate etching. A modified RCA method was used to clean the substrate before each procedure. A thin, thermal oxide layer was grown to passivate the surface and then a thick field oxide was deposited by CVD. The fabricated MESFET showed good contact properties and DC/RF performances. The maximum oscillation frequency of 34 GHz and the cut-off frequency of 9.3 GHz were obtained. The power gain was 10.1 dB and the output power of 1.4 W was obtained for 1 mm-gate length device at 2 GHz. The fabricated MESFETs showed the charge trapping-free characteristics and were characterized by the extracted small-signal equivalent circuit parameters.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.473-478
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• 2016

In this paper, the MIS(: Metal-Insulator-Semiconductor) Capacitor with the nitrided-oxide by RTP are fabricated to investigate the carrier trap parameters due to avalanche electron injection. Two times turn-around phenomenon of the flatband voltage shift generated by the avalanche injection are observed. This shows that electron trapping occurs in the oxide film at the first stage. As the electron injection increases, the first turn-around occures due to a positive charge in the oxide layer. After further injection, the curves turns around once again by electron captured. Based on the experimental results, the carrier trapping model for system having multi-traps is proposed and is fitting with experimental data in order to determine trap parameter of nitrided-oxide.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.166-173
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• 2009

The reliability of hafnium oxide gate dielectrics incorporating lanthanum (La) is investigated. nMOSFETs with metal/La-doped high-k dielectric stack show lower $V_{th}$ and $I_{gate}$, which is attributed to the dipole formation at the high-k/$SiO_2$ interface. The reliability results well correlate with the dipole model. Due to lower trapping efficiency, the La-doping of the high-k gate stacks can provide better PBTI immunity, as well as lower charge trapping compared to the control HfSiO stacks. While the devices with La show better immunity to positive bias temperature instability (PBTI) under normal operating conditions, the threshold voltage shift (${\Delta}V_{th}$) at high field PBTI is significant. The results of a transconductance shift (${\Delta}G_m$) that traps are easily generated during high field stress because the La weakens atomic bonding in the interface layer.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.2
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• Transactions on Electrical and Electronic Materials
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• v.11 no.4
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• pp.155-165
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• 2010

As a promising candidate to replace the conventional floating gate flash memories, polysilicon-oxide-nitride-oxidesilicon (SONOS)-type nonvolatile semiconductor memories have been investigated widely in the past several years. SONOS-type memories have some advantages over the conventional floating gate flash memories, such as lower operating voltage, excellent endurance and compatibility with standard complementary metal-oxide-semiconductor (CMOS) technology. However, their operating speed and date retention characteristics are still the bottlenecks to limit the applications of SONOS-type memories. Recently, various approaches have been used to make a trade-off between the operating speed and the date retention characteristics. Application of high-k dielectrics to SONOS-type memories is a predominant route. This article provides the state-of-the-art research progress of high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories. It begins with a short description of working mechanism of SONOS-type memories, and then deals with the materials' requirements of high-k dielectrics used for SONOS-type memories. In the following section, the microstructures of high-k dielectrics used as tunneling layers, charge trapping layers and blocking layers in SONOS-type memories, and their impacts on the memory behaviors are critically reviewed. The improvement of the memory characteristics by using multilayered structures, including multilayered tunneling layer or multilayered charge trapping layer are also discussed. Finally, this review is concluded with our perspectives towards the future researches on the high-k dielectrics applicable to SONOS-type nonvolatile semiconductor memories.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.94-95
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• 2007

In this paper, the dependence of electrical characteristics of Silicon-$Al_2O_3$-Nitride-Oxide-Silicon (SANOS) memory cell transistors and program speed, reliability of memory device on interface trap between Si substrate and tunneling oxide was investigated. The devices were fabricated by the identical processing in a single lot except the deposition method of the charge trapping layer, nitride. In the case of P/E speed, it was shown that P/E speed is slower in the SONOS cell transistors with larger interface trap density by charge blocking effect, which is confirmed by simulation results. However, the data retention characteristics show much less dependence on interface trap. Therefore, to improve SANOS memory characteristic, it is very important to optimize the interface trap and charge trapping layer.