• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.7
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• pp.1363-1374
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• 2009

This paper reviews the characteristics and technical trends in Power MOSFET technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits. The technology challenges involved in combining power handling capability with finger gate, trench array, super junction structure, and SiC transistor are described, together with examples of solutions for telecommunications, motor control, and switch mode power supplies.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.6
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• pp.546-550
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• 2013

We propose a novel negative differential resistance (NDR) device with ultra-high peak-to-valley current ratio (PVCR) by combining pn junction diode with depletion mode nanowire (NW) transistor, which suppress the valley current with transistor off-leakage level. Band-to-band tunneling (BTBT) Esaki diode with degenerately doped pn junction can provide multiple switching behavior having multi-peak and valley currents. These multiple NDR characteristics can be controlled by doping concentration of tunnel diode and threshold voltage of NW transistor. By designing our NDR device, PVCR can be over $10^4$ at low operation voltage of 0.5 V in a single peak and valley current.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.06a
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• pp.3-4
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• 2009

As device process technology advances, effective channel length, the thickness of gate oxide, and supply voltage decreases. This paper describes a novel electrostatic discharge (ESD) protection device which has current feedback for high ESD immunity. A conventional Gate-Grounded NMOS (GGNMOS) transistor has only one ESD current path, which makes, the core circuit be in the safe region, so an GGNMOS transistor has low current immunity compared with our device which has current feedback path. To simulate our device, we use conventional $0.18\;{\mu}m$ technology parameters with a gate oxide thickness of $43\;{\AA}$ and power supply voltage of 1.8 V. Our simulation results indicate that the area of our ESD protection, device can be smaller than a GGNMOS transistor, and ESD immunity is better than a GGNMOS transistor.

• Proceedings of the Korean Magnestics Society Conference
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• 2003.06a
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• pp.24-24
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• 2003

Metallic magnetoelectronic devices have studied intensively and extensively for last decade because of the scientific interest as well as great technological importance. Recently, the scientific activity in spintronics field is extending to the hybrid devices using ferromagnetic/semiconductor heterostructures and to new ferromagnetic semiconductor materials for future devices. In case of the hybrid device, conductivity mismatch problem for metal/semiconductor interface will be able to circumvent when the device operates in ballistic regime. In this respect, spin-valve transistor, first reported by Monsma, is based on spin dependent transport of hot electrons rather than electron near the Fermi energy. Although the spin-valve transistor showed large magnetocurrent ratio more than 300%, but low transfer ratio of the order of 10$\^$-5/ prevents the potential applications. In order to enhance the collector current, we have prepared magnetic tunneling transistor (MTT) with single ferromagnetic base on Si(100) collector by magnetron sputtering process. We have changed the resistance of tunneling emitter and the thickness of baser layer in the MTT structure to increase collector current. The high transfer ratio of 10$\^$-4/ range at bias voltage of more than 1.8 V, collector current of near l ${\mu}$A, and magnetocurrent ratio or 55% in Si-based MTT are obtained at 77K. These results suggest a promising candidate for future spintronic applications.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.310-311
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• 2009

New X-shaped crystalline molecules have been synthesized through various coupling reactions and their electronic properties were investigated. They exhibit good solubility in common organic solvents and good self-film forming properties. They are intrinsically crystalline as they exhibit well-defined X-ray diffraction patterns from uniform and preferred orientations of molecules. They also exhibited high field effect mobilities in thin film transistor (TFT) and good device performances.

• 제어로봇시스템학회:학술대회논문집
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• 2000.10a
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• pp.510-510
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• 2000

This paper introduces the design of BiCMOS latched comparator circuit for high-speed system application, which can be used in data conversion, instrumentation, communication system etc. By exploiting the advantage technology of the combination of both the bipolar transistor and the CMOS transistor devices. The comparator circuit includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. The resistive load of conventional current-steering comparator is replaced by a load, which is made by a NMOS transistor. The advantage of design and PSPICE simulation of BiCMOS latched comparator are the circuit will obtain wide bandwidth with lowest power consumption at a single supply voltage. All the characteristics of the proposed BiCMOS latched comparator circuit is carried out by simulation program.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.583-584
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• 2006

This paper presents transistor matching in 70 nm nMOS. To adopt radio frequency(RF) applications, the RF performance, especially the current gain cutoff frequency($f_T$), is examined experimentally through a wafer. It is proved that the RF performance variation of 70 nm nMOS is dependent to the device geometry, the total width(W). The RF performance variation of 70 nm nMOS is inversely proportional to square root of total width(W). Also, decreasing of the number of fingers($N_f$) is helpful to decrease the variation of 70 nm nMOS.

• Journal of the Korean Magnetics Society
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• v.21 no.2
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• pp.67-76
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• 2011

Semiconductor spintronics is an emerging interdisciplinary technology based on the electron spin degree of freedom, combining the magnetic materials and semiconductors. The spin transistor represents a novel semiconductor device, in which the electron spin is injected, manipulated, and detected, and thereby a memory function and data processing function are enabled in one device. Particularly, the spin transistor based on Silicon, the mainstream semiconductor, might have a significant impact on information technology. This review introduces the major progresses of Silicon spintronics in recent years, and describes the technical issues for the future.

• The KIPS Transactions:PartA
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• v.17A no.3
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• pp.121-126
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• 2010

This paper proposes a low-power MOS current-mode logic circuit with the low voltage swing technology and the high-threshold sleep-transistor. The sleep-transistor is used to high-threshold voltage PMOS transistor to minimize the leakage current. The $16{\times}16$ bit parallel multiplier is designed by the proposed circuit structure. Comparing with the conventional MOS current-model logic circuit, the circuit achieves the reduction of the power consumption in sleep mode by 1/104. The proposed circuit is achieved to reduce the power consumption by 11.7% and the power-delay-product by 15.1% compared with the conventional MOS current-model logic circuit in the normal mode. This circuit is designed with Samsung $0.18\;{\mu}m$ standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.9 no.1
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• pp.120-131
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• 2016

In this paper, a 512b MTP memory IP is designed by using MTP memory cells which are written by the FN (Fowler-Nordheim) tunneling method with only MV (medium voltage) devices of 5V which uses the back-gate bias, that is VNN (negative voltage). The used MTP cell consists of a CG (control gate) capacitor, a TG (tunnel gate) transistor, and a select transistor. To reduce the size of the MTP memory cell, just two PWs (P-wells) are used: one for the TG and the select transistors; and the other for the CG capacitor. In addition, just one DNW (deep N-well) is used for the entire 512b memory cell array. VPP and VNN generators supplying pumping voltages of ${\pm}8V$ which are insensitive to PVT variations since VPP and VNN level detectors are designed by a regulated voltage, V1V (=1V), provided by a BGR voltage generator.