• Journal of IKEEE
• /
• v.12 no.3
• /
• pp.172-175
• /
• 2008

An improved triangular/square-wave VCO using OTAs is presented. It consists of two OTAs, a timing capacitor, and a resistor. A prototype circuit built with commercially available components exhibits less than 0.01% nonlinearity in its current-to-frequency transfer characteristic from 0.2 to 14 kHz and 450 ppm/$^{\circ}C$ temperature coefficient of frequency over $-20^{\circ}C$ to $40^{\circ}$.

• Proceedings of the IEEK Conference
• /
• 2002.07a
• /
• pp.333-336
• /
• 2002

An alternative CMOS implementation of a multi-output four-terminal floating nullor (FTFN) with constant-g$_{m}$ rall-to-rail input stage is proposed. This presented circuit is based on the advantages of a complementary transconductance amplifier and class AB dual translinear cell circuit that comes up with wide bandwidth. The constant-g$_{m}$ characteristic is controlled by the maximum-current selection circuits, maintaining the smooth response over the change of input common mode voltage. The circuit performances are confirmed through HSPICE simulations. A current-mode multifunction filter is used to exhibit the potentiality of this proposed scheme.eme.

• Journal of electromagnetic engineering and science
• /
• v.8 no.3
• /
• pp.114-118
• /
• 2008

Direct-conversion RF front-end for 5-GHz WLAN is implemented in $0.18-{\mu}m$ CMOS technology. The front-end consists of a low noise amplifier, and low flicker noise down-conversion mixers. For the mixer, an inductor is included to resonate out parasitic tail capacitances in the transconductance stage at the operating frequency, thereby improves the flicker noise performance of the mixer, and the overall noise performance of the front-end. The receiver RF front-end has 6.5 dB noise figure, - 13 dBm input IP3, and voltage conversion gain of 20 dB with the power consumption of 30 mW.

• Transactions on Electrical and Electronic Materials
• /
• v.14 no.6
• /
• pp.291-294
• /
• 2013

When subjected to a change in dimensions, the device performance decreases. Multi-gate SOI devices, viz. the Double Gate MOSFET (DG-MOSFET), are expected to make inroads into integrated circuit applications previously dominated exclusively by planar MOSFETs. The primary focus of attention is how channel engineering (i.e. Graded Channel (GC)) and gate engineering (i.e. Dual Insulator (DI)) as gate oxide) creates an effect on the device performance, specifically, leakage current ($I_{off}$), on current ($I_{on}$), and DIBL. This study examines the performance of the devices, by virtue of a simulation analysis, in conjunction with N-channel DG-MOSFETs. The important parameters for improvement in circuit speed and power consumption are discussed. From the analysis, DG-DI MOSFET is the most suitable candidate for high speed switching application, simultaneously providing better performance as an amplifier.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
• /
• v.25 no.9
• /
• pp.686-691
• /
• 2012

In this paper, we designed a Chua's chaotic circuit using transcondcutor based nonlinear resistor. Proposed chaotic circuit consist of L, C, R and transcondcutor based Chua's diode. We performed SPICE simulation for chaotic dynamics such as time seriesform, frequency analysis and phase plane of the circuit. Chaotic dynamics of the circuit was analysed according to MOS size variation of the operational transconductance amplifier. Also, we performed SPICE circuit analysis for temperature dependance of the circuit. SPICE results showed that chaotic dynamics of the circuit varied according to the temperature variation and chaotic signals were generated in specific temperature conditions.

• Proceedings of the IEEK Conference
• /
• 2008.06a
• /
• pp.547-548
• /
• 2008

Linearity improvement technique of transconductor is presented in the paper. In order to certify the linearity improvement of proposed transconductor, the 3rd-order Elliptic low-pass Gm-C filter which provides 5MHz cutoff is implemented by using the transconductor. According to the IIP3 measurement result of filters, proposed filter has higher IIP3 than normal source-degeneration filter; the In-band IIP3 of proposed and normal filter are 10.1 dBm and 7.5 dBm respectively. The filter is fabricated in 1P6M $0.18-{\mu}m$ CMOS while consuming the 3.3mW with 1.8 Vdd. The in-band input-referred noise voltage is $62.3{\mu}Vrms$ and the SFDR is 54.1 dB.

• Proceedings of the IEEK Conference
• /
• 2002.07b
• /
• pp.759-762
• /
• 2002

In this paper, a voltage-controlled linear variable resistor (VCLVR) using a floating-gate MOS-FET (FG-MOSFET) is proposed. The proposed-circuit is the grounded VCLVR consists of only an ordinary MOSFET and an FG-MOSFET. The advantage of the proposed VCLVR are low-voltage and wide-input range. Next, as applications, a floating-node voltage controlled variable resistor and an operational transconductance amplifier using the proposed VCLVRs are proposed. The performance of the proposed circuits are characterized through HSPICE simulations with a standard 0.6 ${\mu}$m CMOS process. simulations of the proposed VCLVR demonstrate a resistance value of 40 k$\Omega$ to 338 k$\Omega$ and a THD of less than 1.1 %.

• Proceedings of the Optical Society of Korea Conference
• /
• 1991.06a
• /
• pp.190-193
• /
• 1991

The monolithically integrated receiver OEIC using InGaAs/InP PIN PD, junction FET's and bias resistor has been fabricated on semi-insulating InP substrate. The fabrication process is highly compatible between PD and self-aligned JFET, and reduction in gate length is achieved using an anisotropic selective etching and a non-planar OMVPE process. The PIN photodetector with a 80 ${\mu}{\textrm}{m}$ diameter exhibits current of less than 5 nA and a capacitance of about 0.35 pF at -5 V bias voltage. An extrinsic transconductance and a gate-source capacitance of the JFET with 4 ${\mu}{\textrm}{m}$ gate length (gate width = 150 ${\mu}{\textrm}{m}$) are typically 45 mS/mm and 0.67 pF at 0 V, respectively. A voltage gain of the pre-amplifier is 5.5.

• Proceedings of the KIEE Conference
• /
• 1990.07a
• /
• pp.525-528
• /
• 1990

In this paper, a CMOS Operational Transconductance Amplifier (OTA) which is used for high-frequency operation has been designed and simulated by SPICE 2G program. To increase input linear range, the input stage is designed by cross-coupled pair. And the output stage insert buffer stage for the buffing and gain. The band-width of designed OTA is $50{\sim}60$ [MHz].

• Proceedings of the IEEK Conference
• /
• 2000.07a
• /
• pp.159-162
• /
• 2000

Novel simulated floating inductor (SFI) using fully-differential operational transconductance amplifier (FOTA) is presented. The SFI only consists of two FOTA and a capacitor. A ladder-type third-order elliptic low-pass filter is also presented for the SFI’s application. The theory of operations described and the simulation results are used to verify theoretical predictions. The SFI shows close agreement between predicted behavior and simulation performance. The simulation results that the SFI have The temperature coefficient of-179 ppm/$^{\circ}C$ and Q factor of 120 at 200kHz at supply voltage ${\pm}$5 V.