• Title/Summary/Keyword: Transconductance amplifier

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V-Band Power Amplifier MMIC with Excellent Gain-Flatness (광대역의 우수한 이득평탄도를 갖는 V-밴드 전력증폭기 MMIC)

  • Chang, Woo-Jin;Ji, Hong-Gu;Lim, Jong-Won;Ahn, Ho-Kyun;Kim, Hae-Cheon;Oh, Seung-Hyueb
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.623-624
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    • 2006
  • In this paper, we introduce the design and fabrication of V-band power amplifier MMIC with excellent gain-flatness for IEEE 802.15.3c WPAN system. The V-band power amplifier was designed using ETRI' $0.12{\mu}m$ PHEMT process. The PHEMT shows a peak transconductance ($G_{m,peak}$) of 500 mS/mm, a threshold voltage of -1.2 V, and a drain saturation current of 49 mA for 2 fingers and $100{\mu}m$ total gate width (2f100) at $V_{ds}$=2 V. The RF characteristics of the PHEMT show a cutoff frequency, $f_T$, of 97 GHz, and a maximum oscillation frequency, $f_{max}$, of 166 GHz. The gains of the each stages of the amplifier were modified to have broadband characteristics of input/output matching for first and fourth stages and get more gains of edge regions of operating frequency range for second and third stages in order to make the gain-flatness of the amplifier excellently for wide band. The performances of the fabricated 60 GHz power amplifier MMIC are operating frequency of $56.25{\sim}62.25\;GHz$, bandwidth of 6 GHz, small signal gain ($S_{21}$) of $16.5{\sim}17.2\;dB$, gain flatness of 0.7 dB, an input reflection coefficient ($S_{11}$) of $-16{\sim}-9\;dB$, output reflection coefficient ($S_{22}$) of $-16{\sim}-4\;dB$ and output power ($P_{out}$) of 13 dBm. The chip size of the amplifier MMIC was $3.7{\times}1.4mm^2$.

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Control Design of the Boost Converters for LED Backlights Driving (LED 백라이트 구동을 위한 승압 전력변환 제어기 설계)

  • Jeong, Jee-Wook;Park, Hee-Wan;Chon, Hyun-Son;Kim, Tae-Woo;Park, Sin-Kyun
    • Proceedings of the KIPE Conference
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    • 2011.11a
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    • pp.7-9
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    • 2011
  • 본 논문은 LED 백라이트 구동을 위한 전력변환 제어기 설계 및 동특성에 대해 설명한다. 또한 근래 산업계에서 널리 사용하는 operational transconductance amplifier(OTA)와 operational amplifier(op-amp)의 상관관계를 분석하여 각각의 소자를 이용한 최적 제어기를 설계하였다. 설계와 해석을 위해 PSIM 시뮬레이션을 사용하였으며 구현한 PSIM 모델은 실험을 통하여 타당성을 증명하였다.

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Electronically adjustable gain instrumentation amplifier

  • Julprapa, A.;Chaikla, A.;Ukakimaparn, P.;Parnklang, J.;Suphap, S.;Reiwruja, V.
    • 제어로봇시스템학회:학술대회논문집
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    • 2001.10a
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    • pp.158.3-158
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    • 2001
  • In this paper, an instrumentation amplifier, which the voltage gain can be electronically adjusted, is proposed. The realization method is based on the use of operational transconductance amplifiers (OTAs) as active circuit elements. The common mode rejection ratio (CMRR) of the proposed scheme is better than 93dB at the frequency of about 70kHz. The temperature effect to the circuit performance is also compensated. Experimental and simulation results demonstrating the characteristics of the proposed scheme are also included.

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CMOS Realization of VDTA-Gm and its Application on Filter Circuits (VDTA-Gm 회로의 CMOS 구현 및 필터 응용)

  • Bang, Jun-Ho;Basnet, Barun;Kim, Jung-Hun;Kim, Hoyoung;Oh, Ildae
    • Proceedings of the KIEE Conference
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    • 2015.07a
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    • pp.1535-1536
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    • 2015
  • CMOS realization of VDTA (Voltage Differencing Transconductance Amplifier) - Gm and its application in the design of multifunctional filter is presented. Small signal analysis is also done to simplify and depict the realization method. Also the parameters and can be tuned by adjusting the circuit components. The performance of VDTA-Gm amplifier and the designed Band Pass filter are simulated using HSPICE with CMOS $0.18{\mu}m$ process parameters.

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A Novel Adaptive Biasing Scheme for CMOS Op-Amps

  • Kurkure Girish;Dutta Aloke K.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.3
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    • pp.168-172
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    • 2005
  • In this paper, we present a new adaptive biasing scheme for CMOS op-amps. The designed circuit has been used in an Operational Transconductance Amplifier (OTA) with ${\pm}1$ V power supply, and it has improved the positive and negative slew rates from 2.92 V/msec to 1242 V/msec and from 1.56 V/msec to 133 V/msec respectively, while maintaining all the small-signal performance parameter values the same as that without adaptive biasing (as expected), however, there was a marginal decrease of the dynamic range. The most useful features of the proposed circuit are that it uses a very low number of components (thus not creating severe area penalty) and requires only 25 nW of extra stand-by power.

A Dual-Band CMOS Low-Noise Amplifier

  • Oh, Tae-Hyoun;Jun, Hee-Suk;Jung, Yung-Ho;Shin, Hyung-Cheol
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.489-490
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    • 2006
  • This paper presents a switch type 2.4/5.8 GHz dual band low-noise amplifier, designed with $0.13{\mu}m$ RF CMOS technology. Using MOS switch allows the LNA to have two different input transconductance and output capacitance modes. Given supply voltage of 1.2 V, the simulation exhibits gains of 8.1 dB and 17.1 dB, noise figures of 3.1 dB and 2.57 dB and power consumptions of 13.0 mW and 10.2 mW at 2.4 GHz and 5.8 GHz, respectively.

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Development of a Two-Stage High Gain D-Band MMIC Drive Amplifier Using $0.1{\mu}m$ Metamorphic HEMT Technology ($0.1{\mu}m$ Metamorphic HEMT를 이용한 고이득 D-Band MMIC 2단 구동증폭기 개발)

  • Lee, Bok-Hyung;Rhee, Jin-Koo
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.45 no.12
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    • pp.41-46
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    • 2008
  • We report a high gain D-band(110 - 140 GHz) MMIC drive amplifier based on $0.1{\mu}m$ InGaAs/InAlAs/GaAs metamorphic HEMT technology. The amplifier shows an excellent $S_{21}$ gain characteristic greater than 10 dB in a millimeterwave frequency of 110 GHz, Also the amplifier has good reflection characteristics of a $S_{11}$ of -3.5 dB and a $S_{22}$ of -6.5 dB at 110 GHz, respectively The high performances of the MMIC drive amplifier is mainly attributed to the characteristics of the MHEMTs exhibiting a maximum transconductance of 760 mS/mm, a current gain cut-off frequency of 195 GHz and a maximum oscillation frequency of 391 GHz.

Recent Developments in High Resolution Delta-Sigma Converters

  • Kim, Jaedo;Roh, Jeongjin
    • Journal of Semiconductor Engineering
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    • v.2 no.1
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    • pp.109-118
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    • 2021
  • This review paper describes the overall operating principle of a discrete-time delta-sigma modulator (DTDSM) and a continuous-time delta-sigma modulator (CTDSM) using a switched-capacitor (SC). In addition, research that has solved the problems related to each delta-sigma modulator (DSM) is introduced, and the latest developments are explained. This paper describes the chopper-stabilization technique that mitigates flicker noise, which is crucial for the DSM. In the case of DTDSM, this paper addresses the problems that arise when using SC circuits and explains the importance of the operational transconductance amplifier performance of the first integrator of the DSM. In the case of CTDSM, research that has reduced power consumption, and addresses the problems of clock jitter and excess loop delay is described. The recent developments of the analog front end, which have become important due to the increasing use of wireless sensors, is also described. In addition, this paper presents the advantages and disadvantages of the three-opamp instrumentation amplifier (IA), current feedback IA (CFIA), resistive feedback IA, and capacitively coupled IA (CCIA) methods for implementing instrumentation amplifiers in AFEs.

A Design of Bandpass Filter for Body Composition Analyzer (체성분 측정기용 대역통과 필터 설계)

  • Bae, Sung-Hoon;Cho, Sang-Ik;Lim, Shin-Il;Moon, Byoung-Sam
    • Journal of the Institute of Electronics Engineers of Korea SC
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    • v.42 no.5 s.305
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    • pp.43-50
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    • 2005
  • This paper describes some IC(integrated circuits) design and implementation techniques of low power multi-band Gm-C bandpass filter for body composition analyzer. Proposed BPF(bandpass filter) can be selected from three bands(20 KHz, 50 KHz, 100 KHz) by control signal. To minimize die area, a simple center frequency tuning scheme is used. And to reduce power consumption, operational transconductance amplifier operated in the sub-threshold region is adopted. The proposed BPF is implemented with 0.35 um 2-poly 3-metal standard CMOS technology Chip area is $626.42um\;{\times}\;475.8um$ and power consumption is 700 nW@100 KHz.

A Simulation-Based Analog Cell Synthesis with Improved Simulation Efficiency (시뮬레이션 효율을 향상시킨 시뮬레이션 기반의 아날로그 셀 합성)

  • 송병근;곽규달
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.36C no.10
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    • pp.8-16
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    • 1999
  • This paper presents a new simulation-based analog cell synthesis approach with improved simulation efficiency For the hierarchical synthesis of analog cells we developed the sub-circuit optimizers such as current mirror and differential input stage. Each sub-circuit optimizer can be used for synthesis of analog cells such as OTA(operational transconductance amplifier), 2-stage OP-AMP and comparator. To reduce the time spending of the simulation-based synthesis we propose 2-stage searching scheme and simulation data reusing scheme. With those schemes the synthesis time spending of OTA was reduced from 301.05sec to 56.52sec by 81.12%. Since our synthesis system doesn't need other additional physical parameters except SPICE parameters, and is independent of the process and its model level, the time spending to port to other process is minimized. We synthesized OTA and 2-stage OP-AMP respectively with our approach to show its usefulness.

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