• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.10
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• pp.34-39
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• 2016

A low-voltage, low-power analog front-end IC for neural recording implant devices is presented. The proposed IC consists of a low-noise neural amplifier and a programmable active bandpass filter to process neural signals residing in the band of 1 Hz to 5 kHz. The neural amplifier is based on a source-degenerated folded-cascode operational transconductance amplifier (OTA) for good noise performance while the following bandpass filter utilizes a low-power current-mirror based OTA with programmable high-pass cutoff frequencies from 1 Hz to 300 Hz and low-pass cutoff frequencies from 300 Hz to 8 kHz. The total recording analog front-end provides 53.1 dB of voltage gain, $4.68{\mu}Vrms$ of integrated input referred noise within 1 Hz to 10 kHz, and noise efficiency factor of 3.67. The IC is designed using $18-{\mu}m$ CMOS process and consumes a total of $3.2{\mu}W$ at 1-V supply voltage. The layout area of the IC is $0.19 mm^2$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.1-7
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• 2007

Class AB bipolar linear transconductors for high frequency applications ire proposed. They consist of a voltage follower, a resistor, and a current follower. The follower circuits are realized by translinear cells or unity-gain buffers. The proposed transconductors are simulated using an 8 GHz bipolar transistor-arrary parameter. Simulation results show that the transconductor using translinear cells has better linearity than one using unity-gain buffers whereas the latter has better temperature stability and higher input resistance than the former. In order to test their high frequency applicability, the transconductors are used to implement an 4th order IF bandpass filter.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.4
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• pp.267-272
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• 2010

In this paper, a Gm-C LPF utilizing common-mode feedforward (CMFF) CMOS inverter type operational transconductance amplifier (OTA) has been designed and verified by circuit simulations. The CMFF CMOS inverter OTA was optimized for wide input linearity and low current consumption using a standard 0.18 ${\mu}m$ CMOS process; gm of 100 ${\mu}S$ and current of 100 ${\mu}A$ at supplied voltage of 1.3 V. Using this optimized CMFF CMOS inverter type OTA, an elliptic 5th order Gm-C LPF for GPS specifications was designed. Gain and frequency tuning of the LPF was done by changing the internal supply voltages. The designed Gm-C LPF gave pass-band ripple of 1.6 dB, stop-band attenuation of 60.8 dB, current consumption of 0.60 mA at supply voltage of 1.2 V. The gain and frequency characteristics of designed Gm-C LPF was unchanged even though the input common-mode voltage is varied.

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.251-263
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• 2008

In this paper, we report an analytical modeling and 2-D Synopsys Sentaurus TCAD simulation of ion implanted silicon carbide MESFETs. The model has been developed to obtain the threshold voltage, drain-source current, intrinsic parameters such as, gate capacitance, drain-source resistance and transconductance considering different fabrication parameters such as ion dose, ion energy, ion range and annealing effect parameters. The model is useful in determining the ion implantation fabrication parameters from the optimization of the active implanted channel thickness for different ion doses resulting in the desired pinch off voltage needed for high drain current and high breakdown voltage. The drain current of approximately 10 A obtained from the analytical model agrees well with that of the Synopsys Sentaurus TCAD simulation and the breakdown voltage approximately 85 V obtained from the TCAD simulation agrees well with published experimental results. The gate-to-source capacitance and gate-to-drain capacitance, drain-source resistance and trans-conductance were studied to understand the device frequency response. Cut off and maximum frequencies of approximately 10 GHz and 29 GHz respectively were obtained from Sentaurus TCAD and verified by the Smith's chart.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.8
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• pp.575-581
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• 2013

The self-cascode (SC) structure has low output voltage swing and high output resistance. In order to implement a simple and better SC structure, the native-$V_{th}$ MOSFETs which has low threshold voltage($V_{th}$) is applied. The proposed SC structure is designed using a qualified industry standard $0.18-{\mu}m$ CMOS technology. Measurement results show that the proposed SC structure has higher transconductance as well as output resistance than single MOSFET. In addition, analog building blocks (e.g. current mirror, basic amplifier circuits) with the proposed SC structure are investigated using by Cadence Spectre simulator. Simulation results show improved electrical performances.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.11
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• pp.126-134
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• 1990

In order to implement high-speed data acquistion system in CMOS VLSI technology, means must be found to overcome the relatively low transconductance and large device mismatch characteristic of MOS device. Because of these device limitations, circuit design approaches tradition-ally used in high-speed bipolar analog-to-digital converter(ADC) are suited to CMOS implementation. Also the design of VLSI CMOS comparator wherein voltage comparision is accomplished by means of a pipelined cascade RSA (Regenerative Sense Amplifier). So, in this paper we designed the A/D converter incorporates the pipelined CMOS comparator.

• Journal of IKEEE
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• v.20 no.3
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• pp.318-321
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• 2016

As IoT industry are growing fast, The importance of power management system is also being magnified. CMOS High power-supply rejection ratio(PSRR) Low-dropout(LDO) regulator is achieved by the proposed ripple Subtractor, Feed-forward capacitor and OTA in this paper. The LDO is implemented in $0.18-{\mu}m$ CMOS technology. With the proposed structures, in the maximum loading of 40mA, Simulation result achieves PSRR of -73.4dB at 500kHz and PSRR better than -40dB when frequency is below 10MHz with $6.8-{\mu}F$ output capacitor.

• Journal of Korea Society of Digital Industry and Information Management
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• v.20 no.2
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• pp.63-74
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• 2024

This Paper presents a resistive wideband fully differential low-noise amplifier (LNA) designed using a noise-cancellation technique for TV tuner applications. The front-end of the LNA employs a cascode common-gate (CG) configuration, and cross-coupled local feedback is employed between the CG and common-source (CS) stages. The moderate gain at the source of the cascode transistor in the CS stage is utilized to boost the transconductance of the cascode CG stage. This produces higher gain and lower noise figure (NF) than a conventional LNA with inductor. The NF can be further optimized by adjusting the local open-loop gain, thereby distributing the power consumption among the transistors and resistors. Finally, an optimized DC gain is obtained by designing the output resistive network. The proposed LNA, designed in SK Hynix 180 nm CMOS, exhibits improved linearity with a voltage gain of 10.7 dB, and minimum NF of 1.6-1.9 dB over a signal bandwidth of 40 MHz to 1 GHz.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.11
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• pp.21-27
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• 2004

In this paper, millimeter-wave monolithic integrated circuit(MIMIC) low noise amplifier(LNA) for V-band, which is applicable to 60 GHz wireless local area network(WLAN), was fabricated using the high performance 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-gate pseudomorphic high electron mobility transistor(PHEMT). The DC characteristics of PHEMT are drain saturation current density(Idss) of 450 mA/mm and maximum transconductance(gm, max) of 363.6 mS/mm. The RF characteristics were obtained the current gain cut-off frequency(fT) of 113 GHz and the maximum oscillation frequency(fmax) of 180 GHz. V-band MIMIC LNA was designed using active and passive device library, which is composed of 0.1 ${\mu}{\textrm}{m}$ $\Gamma$-gate PHEMT and coplanar waveguide(CPW) technology. The designed V-band MIMIC LNA was fabricated using integrated unit processes of active and passive device. The measured results of V-band MIMIC LNA are shown S21 gain of 21.3 dB, S11 of -10.6 dB at 60 GHz and S22 of -29.7 dB at 62.5 GHz. The measured result of V-band MIMIC LNA was shown noise figure (NF) of 4.23 dB at 60 GHz.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4B
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• pp.365-371
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• 2002

In this paper, the fabricated power PHEMT devices for millimeter-wave that is below a gate-length of 0.2 $\mu\textrm{m}$ using electronic beam lithography technologies, and the DC and frequency characteristics and an output power characteristics were Measured at the various bias conditions. The unit process that is used in PHEMT's manufacture used that low-resistance ohmic contact, air-bridge and back-side lapping process technologies, and so on. The fabricated power PHEMT have an S521 gain of 4 dB and a maximum transconductance(gm) of 317 mS/mm, an unilateral current gain(fT) of 62 GHz, a maximum oscillation frequency(fmax) of 120 GHz at 35 GHz, and a maximum power output(Pmax) of 16 dBm, a power gain(GP) of 4 dB and a drain efficiency(DE) of 35.5 %.