• Title/Summary/Keyword: Trace Algorithm

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A New trace-driven Simulation Algorithm for Sector Cache Memories with Various Block Sizes (다양한 블럭 크기를 갖는 섹터 캐시 메모리의 Trace-driven 시뮬레이션 알고리즘)

  • Dong Gue Park
    • Journal of the Korean Institute of Telematics and Electronics B
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    • v.32B no.6
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    • pp.849-861
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    • 1995
  • In this paper, a new trace driven simulation algorithm is proposed to evaluate the bus traffic and the miss ration of the various sector cache memories, which have various sub-block sizes and block sizes and associativities and number of sets, with a single pass through an address trace. Trace-driven simulaton is usually used as a method for performance evaluation of sector cache memories, but it spends a lot of simulation time for simulating the diverse cache configurations with a long address trace. The proposed algorithm shortens the simulation time by evaluating the performance of the various sector cache configurations. which have various sub-block sizes and block sizes and associativities and number of sets , with a single pass through an address trace. Our simulation results show that the run times of the proposed simulation algorithm can be considerably reduced than those of existing simulation algorithms, when the proposed algorithm is miplemented in C language and the address traces obtained from the various sample programs are used as a input of trace-driven simulation.

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Low-Power Systolic Array Viterbi Decoder Implementation With A Clock-gating Method (Clock-gating 방법을 사용한 저전력 시스톨릭 어레이 비터비 복호기 구현)

  • Ryu Je-Hyuk;Cho Jun-Dong
    • The KIPS Transactions:PartA
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    • v.12A no.1 s.91
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    • pp.1-6
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    • 2005
  • This paper presents a new algorithm on low power survivor path memory implementation of the trace-back systolic array Viterbi algorithm. A novel idea is to reuse the already-generated trace-back routes to reduce the number of trace-back operations. And the spurious switching activity of the trace-back unit is reduced by making use of a clock gating method. Using the SYNOPSYS power estimation tool, DesignPower, our experimental result shows the average $40{\%}$ power reduction and $23{\%}$ area increase against the trace-back unit introduced in [1].

A New Trace Calculation Algorithm on Trinomial Irreducible Polynomial of RS code (RS-부호에 유용한 3항 기약 다항식에서 새로운 TRACE 연산 알고리즘)

  • Seo, Chang-Ho;Eun, Hui-Cheon
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.1
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    • pp.75-80
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    • 1995
  • In this paper, we show that it is more efficient to use a new algorithm than to use a method of trace definition and property when we use trace calculation method on trinomial irreducible polynomial of reed-solomon code. This implementation has been done in SUN SPARC2 workstation using C-language.

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A Hierarchical and Incremental DRC System Using Sliced-Edge Trace Algorithm (Sliced-Edge Trace 알고리듬을 이용한 계층적 Incremental DRC 시스템)

  • 문인호;김현정;오성환;황선영
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.28A no.1
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    • pp.60-73
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    • 1991
  • This paper presents an efficient algorithm for incremental and hierarchical design rule checking of VLSI layouts, and describes the implementation of a layout editor using the proposed algorithm. Tracing the sliced edges divided by the intersection of the edges either ina polygon or in two polygons (Sliced-Edge Trace), the algorithm performs VLSI pattern operations like resizing and other Boolean operations. The algorithm is not only fast enough to check the layouts of full-custom designs in real-time, but is general enough to be used for arbitrarily shaped polygons. The proposed algorithm was employed in developingt a layout editor on engineering workstations running UNIX. The editor has been successfully used for checking, generating and resizing of VLSI layouts.

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The Trace Algorithm of Mobile Robot Using Neural Network (신경 회로망을 이용한 Mobile Robot의 추종 알고리즘)

  • 남선진;김성현;김성주;김용민;전홍태
    • Proceedings of the Korean Institute of Intelligent Systems Conference
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    • 2001.12a
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    • pp.267-270
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    • 2001
  • In this paper, we propose the self-autonomous algorithm for mobile robot system. The proposed mobile robot system which is teamed by learning with the neural networks can trace the target at the same distances. The mobile robot can evaluate the distance between robot and target with ultrasonic sensors. By teaming the setup distance, current distance and command velocity, the robot can do intelligent self-autonomous drive. We use the neural network and back-propagation algorithm as a tool of learning. As a result, we confirm the ability of tracing the target with proposed mobile robot.

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Intelligent Trace Algorithm of Mobile Robot Using Fuzzy Logic

  • Kim, Jong-Soo;Kim, Seong-Joo;Jeon, Hong-Tae
    • Proceedings of the IEEK Conference
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    • 2002.07c
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    • pp.1658-1661
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    • 2002
  • In this paper, we propose the intelligent inference trace algorithm of the mobile robot using fuzzy logic. With the proposed algorithm, the mobile robot can trace human at regular intervals. The mobile robot can recognize the distances between it and human with both multi-ultrasonic sensors and PC-camera and then, can inference the direction and velocity of itself to keep the given regular distances. In the first, the mobile robot acquires the information about circumstances using ultrasonic sensor and PC-camera then secondly, recognize the status of circumstances using the fuzzy logic. We also evaluate the experimental navigation test at several times to verify the ability of the fuzzy logic controller.

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Modelling and performance analysis for the end-to-end path tracing managment in ATM network (ATM망의 단대단 통신로 추적관리의 모델링 및 성능분석)

  • 박명환;안중영;조규섭
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.9
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    • pp.2385-2401
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    • 1996
  • In this paper, a management model and a path trace algorithm are proposed for the end-to-end path tracing management in ATM network. Proposedmodel is based on the TINA(Telecommunication Information Networking Architecture) and computational object(CO) of ODP(Open Distributed Processing).We related computational object for the path trace to another computational object which covers the ATM routing and established operational procedure according to this relationship. This procedure identifies the end-to-end by way of tracing the ATM connections then collect identification information on the that path. End-to-end trace is performed on the network management level. Broadcasting-with-synchronized-control and GTM(Global Ticket Method) are proposed as path trace algorithm considering the real time properties and data ingetrity. Computer simulations are also performed to evaluate the performance of the proposed algorithm and its resuls are shown in this paper.

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A Verification of Intruder Trace-back Algorithm using Network Simulator (NS-2) (네트워크 시뮬레이터 도구를 이용한 침입자 역추적 알고리즘 검증)

  • Seo Dong-il;Kim Hwan-kuk;Lee Sang-ho
    • Journal of KIISE:Information Networking
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    • v.32 no.1
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    • pp.1-11
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    • 2005
  • Internet has become an essential part of our daily lives. Many of the day to day activities can already be carried out over Internet, and its convenience has greatly increased the number of Internet users. Hut as Internet gains its popularity, the illicit incidents over Internet has also proliferated. The intruder trace-back technology is the one that enables real time tracking the position of the hacker who attempts to invade the system through the various bypass routes. In this paper, the RTS algorithm which is the TCP connection trace-back system using the watermarking technology on Internet is proposed. Furthermore, the trace-bark elements are modeled by analyzing the Proposed trace-back algorithm, and the results of the simulation under the virtual topology network using ns-2, the network simulation tool are presented.

Lane Detection Using Moore-Neighbor Edge Trace Algorithm (무어-네이버 에지추적 알고리즘을 이용한 차선검출기법)

  • Kim, Byoung-Hyun;Han, Young-Joon;Hahn, Hern-Soo
    • Proceedings of the IEEK Conference
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    • 2008.06a
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    • pp.857-858
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    • 2008
  • This paper proposes a new fast algorithm that detects the lanes on the road using Moore-Neighbor edge trace algorithm, which traces the edge elements by searching the connectivity in eight direction window. The detected line components are connected if they have the same orientation on the same line. The proposed algorithm is faster than other conventional algorithms since it tests only the connectivities of the line segments. The performance of the proposed algorithm has tested by the experiments to test how fast and accurate.

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Maximal overlap discrete wavelet transform-based power trace alignment algorithm against random delay countermeasure

  • Paramasivam, Saravanan;PL, Srividhyaa Alamelu;Sathyamoorthi, Prashanth
    • ETRI Journal
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    • v.44 no.3
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    • pp.512-523
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    • 2022
  • Random delay countermeasures introduce random delays into the execution flow to break the synchronization and increase the complexity of the side channel attack. A novel method for attacking devices with random delay countermeasures has been proposed by using a maximal overlap discrete wavelet transform (MODWT)-based power trace alignment algorithm. Firstly, the random delay in the power traces is sensitized using MODWT to the captured power traces. Secondly, it is detected using the proposed random delay detection algorithm. Thirdly, random delays are removed by circular shifting in the wavelet domain, and finally, the power analysis attack is successfully mounted in the wavelet domain. Experimental validation of the proposed method with the National Institute of Standards and Technology certified Advanced Encryption Standard-128 cryptographic algorithm and the SAKURA-G platform showed a 7.5× reduction in measurements to disclosure and a 3.14× improvement in maximum correlation value when compared with similar works in the literature.