• Journal of the Korean Society for Precision Engineering
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• v.20 no.7
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• pp.114-119
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• 2003

The aligning between the punch and die governs no only the burr formation characteristics but also the life time of the punch and die in the sheet metal blanking process. There are many ways to adjust the two elements in the general punching systems but in the case of micro punch system, the punch size is reduced to a few tenth of micrometer range and the general aligning methods are almost impossible to apply. The image processing is the most widely used method in micro punch aligning, but in order to apply the method, it needs quite a large space for visionary system to approach the punch-die aligning zone. In this paper, the new punch-die aligning method with using the total capacitance between the punch and die hole is proposed. In this method, the tip surface of the punch tool locates at the same plane of the die surface and the capacitance variation between the two elements are measured. When the center of the two elements are coincided, the capacitance is minimized, but when the align is changed to any direction, the capacitance between the two elements increase. In order to verify the feasibility of this method, the aligning and punching tests was performed.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2002.10a
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• pp.1049-1052
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• 2002

The aligning between the punch and die governs no only the burr formation characteristics but also the life time of the punch and die in the sheet metal blanking process. There are many ways to adjust the two elements in the general punching systems but in the case of micro punch system, the punch size is reduced to a few tenth of micrometer range and the general aligning methods are almost impossible to apply. The image processing is the most widely used method in micro punch aligning, but in order to apply the method, it needs quite a large space for visionary system to approach the punch-die aligning zone. In this paper, the new punch-die aligning method with using the total capacitance between the punch and die hole is proposed. In this method, the tip surface of the punch tool locates at the same plane of the die surface and the capacitance variation between the two elements are measured. When the center of the two elements are coincided, the capacitance is minimized, but when the align Is changed to any direction, the capacitance between the two elements increase. In order to verify the feasibility of this method, the aligning and punching tests was performed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.05a
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• pp.399-402
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• 1999

In this paper, a new method for calculating capacitance in arbitrarily shape structure is Presented. This new approach based on divergence theorem of Gauss\`s law is acheive by Surface-Contacted Element(SCE) for Gaussian surface. To evaluate accurate capacitance value in nonuniform electric field. in two dimensional analysis the interpolation using the elements which contact one nod (PE: Point-Element) or two nod (FE: Face-Element) is employed. Because the elements contacted with surface are very small compared with total elements in analytic model, SCE method has shorter computing time to calculate capacitance. This proposed method is verified by comparing the simulated results with value obtained by analytic method.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.61-72
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• 2005

This paper proposes a method which efficiently allocates decoupling capacitance to reduce power supply noise at the floorplan level. We observe problems of previous approach that the decoupling capacitance of each module was overestimated and the power supply noises of modules were changed by inserting additional area for decoupling capacitance, and then suggest a new approach. And, we also present a simple heuristic method which can effectively allocate white space modules for decoupling capacitance area within more faster time instead of LP technique. Experimental results show that our approach can reduce the area of decoupling capacitance to average 7.9 percent compared with Zhao's approach in [4]. Therefore both total area and wire length of nniflm result are decreased. Also, we confirm that our approach solves well the problem caused by inserting additional area. In execution time comparison, our approach shows average 11.6 percent improvement.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.7
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• pp.19-25
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• 1993

By using the point matching method, the coplanar waveguide shielded by the rectangular waveguide has been analyzed. The particular potential solution of C.P.W has been obtained from the boundary condition by using the point matching method. The line capacitance has been obtained from the total charge of the center conductor per length. The effective dielectric constant and the line impedance have been obtained from the line capacitance of C.P.W.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.890-892
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• 1996

This paper presents a method for optimal placement of series condenser in order to improve the power system transient stability using genetic algorithms(GAs). In applying GAs, this approach utilizes two kinds of strings, one is coded by a binary finite-length for the selection of lines to install series condenser, the other is coded by a real value for the determination of injected condenser capacitance. For the formulation. this paper considers multi-objective function which is the critical energy as decelerating energy in power systems and the total injected condenser capacitance. The proposed method is applied to 9-bus, 18-line, 3-machine model system to show its effectiveness in determining the locations to install series condenser and the series condenser capacitance to be injected, simultaneously.

• Tribology and Lubricants
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• v.11 no.5
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• pp.71-77
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• 1995

The capacitance technique was used to measure the minimum oil film thickness in engine bearing and the central oil film thickness between cam and tappet. This method is based on the measurement of total capacitance of oil film. For the measurement of the oil film thickness between cam and tappet, two surfaces were assumed to be flat and parallel within the Hertzian region and all the measured capacitance originated from this region. Shear rates from the measured minimum oil film thickness are over 10$^{6}$ sec$^{-1}$ in the greater part in both two cases. The minimum oil film thickness in engine bearing is larger than the surface roughness. Between cam and tappet it is mostly smaller than the surface roughness. In spite of the awkward restriction of the reliability of measured oil film thickness, it was known that the capacitance technique makes it possible to measure the oil film thickness in elastohydrodynamic and mixed lubrication regimes as well as in hydrodynamic regime. Therefore, it is also possible to classify the lubrication regimes based on the oil film thickness.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.7
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• pp.684-694
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• 2000

For designing circuits for low power systems, the capacitance is an important factor for the power dissipation. Since the capacitance of a gate is proportional to the area of the gate, we can reduce the total power consumption of a circuit by reducing the total area of gates, where total area is a simple sum of all gate areas in the circuit. To reduce the total area, transistor resizing can be used. While resizing transistors, inserting buffer in the proper position can help reduce the total area. In this paper we propose two methods for concurrent transistor sizing and buffer insertion. One method uses template window simulation and the other uses extrapolation. Experimental results show that concurrent transistor sizing with buffer insertion achieved 10-20% more reduction of the total area than when it was done without buffer insertion and template window simulation is more efficient than extrapolation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.7 no.1
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• pp.7-11
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• 2006

Through SCM modeling, we found that the depletion layer in silicon was of a form of a spherical capacitor with the SCM tip biased. Two-dimensional (2D) finite differential method code with a successive over relaxation (SOR) solver has been developed to model the measurements by SCM of a semiconductor wafer that contains an ion-implanted impurity region. Then, we theoretically analyzed the spherical capacitor and determined the total depleted-volume charge Q, capacitance C, and the rate of capacitance change with bias dC/dV. It is very important to observe the depleted carriers' movement in the silicon layer by applying the bias to the tip. So, we calculated the depleted-volume charge, considering different factors such as tip size, oxide thickness, and applied bias (dc+ac), which have an influence on potential and depletion charges.

• Journal of the Korean Electrochemical Society
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• v.6 no.4
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• pp.255-260
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• 2003

The complex capacitance analysis was performed in order to examine the potential-dependent EDLC characteristics of porous carbon electrodes. The imaginary capacitance profiles $(C_{im}\;vs.\;log\lf)$ were theoretically derived for a cylindrical pore and further extended to multiple pore systems. Two important electrochemical parameters in EDLC can be estimated from the peak-shaped imaginary capacitance plots: total capacitance from the peak area and $\alpha_0$ from the peak position. Using this method, the variation of capacitance and ion conductivity in pores can be traced as a function of electric potential. The electrochemical impedance spectroscopy was recorded on the mesoporous carbon electrode as a function of electric potential and analyzed by complex capacitance method. The capacitance values obtained from the peak area showed a maximum at 0.3V (vs. SCE), which was in accordance with cyclic voltammetry result. The ionic conductivity in pores calculated from the peak position showed a maximum at 0.2 V (vs. SCE), then decreased with an increase in potential. This behavior seems due to the enhanced electrostatic interaction between ion and surface charge that becomes enriched at more positive potentials.