• The KIPS Transactions:PartC
• /
• v.18C no.1
• /
• pp.15-22
• /
• 2011

Usually time synchronization is performed after routing tree is constructed. This thesis proposes a time synchronization algorithm combined with single-flooding routing tree construction algorithm in a single path. TSRA (Time Synchronization Routing Algorithm) uses routing packets to construct a routing tree. Two types of time information are added to the routing packet: one is the packet receiving time, and the other is the packet sending time. Time offset and transmission time-delay between parent node and child node could be retrieved from the added time information using LTS (Lightweight Time Synchronization) algorithm. Then parent node sends the time offset and transmission time to children nodes and children nodes can synchronize their time to the parent node time along the routing tree. The performance of proposed algorithm is compared to the TPSN (Timing-sync Protocol for Sensor Networks) which is known to have high accuracy using NS2 simulation tool. The simulation result shows that the accuracy of time synchronization is comparable to TPSN, the synchronization time of all sensor nodes is faster than TPSN, and the energy consumption is less than TPSN.

• Journal of the Korean Institute of Telematics and Electronics C
• /
• v.36C no.6
• /
• pp.18-26
• /
• 1999

This paper presents the architecture and design of a DSSS MODEM ASIC chip for wireless local area networks (WLAN). The implemented MODEM chip supports the DSSS physical layer specifications of the IEEE 802.11. The chip consits of a transmitter and a receiver which contain a CRC encoder/decoder, a differential encoder/decoder, a frequency offset compensator and a timing recovery circuit. The chip supports various data rates, i.e., 4,2 and 1Mbps and provides both DBPSK and DQPSK for data modulation. We have performed logic synthesis using the $SAMSUNG^{TM}$ $0.6{\mu}m$ gate array library and the implemented chip consists of 53,355 gates. The MODEM chip operates at 44MHz, the package type is 100-pin QFP and the power consumption is 1.2watt at 44MHz. The implemented MODEM architecture shows lower BER compared with the Harris HSP3824.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.24 no.12A
• /
• pp.1876-1882
• /
• 1999

In this paper, we have proposed a FCB detection algorithm for the GSM system which is european cellular standard. The detection algorithm can be implemented using received signal sampler, correlator, and post detection combiner. GSM mobile phone can use the proposed algorithm for detection of the Broadcasting Channel, and to obtain the initial timing estimate. The proposed algorithm has a architecture which is suitable for DSP or ASIC implementation, and required memory size is small. The performance of the algorithm is a function of the processing data window size and the threshold values. Proper window size and the threshold values can be determined by analyzing the correlator and combiner. The proposed algorithm has been implemented using DSP, and the performance was verified using baseband simulation. The simulation assumed frequency offset values of 0ppm and 15ppm with the receiver filter bandwidth set at both minimum and maximum. It is shown that the algorithm is robust under various assumptions, and suitable for real implementations.

• Journal of the Korean Society for Railway
• /
• v.15 no.5
• /
• pp.454-458
• /
• 2012

The CBTC(Communication based Train Control) and WPAN(Wireless Personal Area Network) systems employed on 2.4GHz ISM band wireless networks provide complementary service within the same environment. Coexistence between the networks will be impaired if the mutual packets are uncertainty associated the timing or gaussian distance. This paper analyzes the impact of the mutual interference and proposed method to minimize the effect of the WPAN system signals on CBTC system. The performance analysis is illustrated by examining the symbol error rate versus signal to noise interference ratio in terms of carrier frequency offset. The method contributes to reduce the symbol error rate drastically. However it can't be a fundamental solution for the impact on the interference problem. It may be needed for railway only frequency after checking the problems of the current railway frequency.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2002.11a
• /
• pp.880-883
• /
• 2002

In this paper, we propose the synchronization recovery algorithm which is suitable to wireless multimedia of wireless channel situation which is being used OFDM signaling method. The basic of the suggested clock synchronization. restoration Algorithm is to getting the shock response of channel or getting the multipath strength profile through IFFT after the getting the frequency, response of deducted channel from channel deductor of receiver and to trace the location in the channel energy concentrated area of timing area. And it also analysis the start point of 64-QAM and 16-QAM if the sampling clock offset has the sample of $\pm$1-3, and we identified the occurance of performance deterioration when occures more than 2 samples of offset to compare with star point and BER performance in optimum sampling point result of BER performance checking, and we know that the recovery algorithm proposed algorithm also provide excellent synchronization characteries under frequency, selecting fading channel as result of simulation.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.39C no.3
• /
• pp.264-274
• /
• 2014

Time synchronization becomes a critical issue in underwater acoustic networks (UANets) because nodes cooperate together or individually work by communicating each other in diverse underwater applications. Compared with the time synchronization approaches in terrestrial networks, several intrinsic limitations of UANets (e.g., the unavailability of GPS, long propagation delay, mobility due to currents, limited energy consumption, or low data rate) need to be considered in synchronizing the timing among underwater nodes. For the purpose of developing more efficient time synchronization protocols for UANets, we review the existing approaches, which estimate both the clock offset and the clock skew of underwater nodes. Finally, we outline the state-of-the art time synchronization protocols for UANets by comparing and summarizing them according to their synchronization characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.36 no.8B
• /
• pp.1012-1020
• /
• 2011

In this paper a design of $\pi$/4-DQPSK baseband receiver for the exchange of digital data and e-mail between shore and ship stations and/or among ship stations in the maritime mobile service VHF channels is described. Due to the permitted relatively big frequency instability of local oscillators at the transmitter and the receiver of maritime communication system, the designed baseband receiver should have the capabilities of correct estimation and compensation of the synchronization parameters, such as symbol timing and frequency offset, from the received signal which might include relatively big frequency error. Simulated BER results show that the designed baseband receiver works less than 0.5dB loss under AWGN channel when the normalized frequency offset of the received signal is more then 20%.

• Journal of IKEEE
• /
• v.23 no.3
• /
• pp.800-804
• /
• 2019

This paper presents a dual-loop sub-sampling digital PLL for a 2.4 GHz IoT applications. The PLL initially performs a divider-based coarse lock and switches to a divider-less fine sub-sampling lock. It achieves a low in-band phase noise performance by enabling the use of a high resolution time-to-digital converter (TDC) and a digital-to-time converter (DTC) in a selected timing range. To remove the difference between the phase offsets of the coarse and fine loops, a phase offset calibration scheme is proposed. The phase offset of the fine loop is estimated during the coarse lock and reflected in the coarse lock process, resulting in a smooth transition to the fine lock with a stable fast settling. The proposed digital PLL is designed by SystemVerilog modeling and Verilog-HDL and fully verified with simulations.

• Journal of Communications and Networks
• /
• v.2 no.1
• /
• pp.58-68
• /
• 2000

In this paper we introduce the correlation-aided distributed sample acquisition (CDSA) scheme for fast cell search in IMT-2000 W-CDMA cellular system. The proposed scheme incorporates the state symbol correlation process into the comparison-correction based synchronization process of the original DSA scheme to enable fast acquisition even under very poor channel environment. for its realization, each mobile station (MS) has to store in its memory a set of state sample sequences. which are determined by the long-period scrambling sequences used in the system and the sampling interval of the state samples. CDSA based cell search is carried out in two stages : First, the MS first acquires the slot timing by using the primary synch code (PSC) and then identifies the igniter code which conveys the state samples of the current cell . Secondly. the MS identifies the scrambling code and frame timing by taking the comparison-correction based synchronization approach and, if the identification is not done satisfactorily within preset time. it initiates the state symbol correlation process which correlates the received symbol sequence with the pre-stored state sample sequences for a successful identification. As the state symbol SNR is relatively high. the state symbol correlation process enables reliable synchronization even in very low chip-SNR environment. Simulation results show that the proposed CDSA scheme outperforms the 3GPP 3-step approach, requiring the signal power of about 7 dB less for achieving the same acquisition time performance in low-SNR environments. Furthermore, it turns out very robust in the typical synchronization environment where large frequency offset exists.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.29 no.1A
• /
• pp.65-76
• /
• 2004

In this paper, a novel preamble structure, including a synchronization preamble and a cell search preamble, is proposed for OFDM-based cellular systems. An efficient algorithm for downlink synchronization and cell searching using the preamble is also proposed. The synchronization process includes the initial symbol timing estimation using continuously, or at least, periodically transmitted downlink signal, frame synchronization, the fine symbol timing estimation, and the frequency offset estimation using the synchronization preamble, and the cell identification using the cell searching preamble. Performance of each synchronization and cell searching step is analyzed and the analytic results including the overall performance of the synchronization and cell searching are verified by computer simulation. It is shown that the proposed preamble with the corresponding synchronization and cell searching algorithm can provide very robust synchronization and cell searching capability even in bad cellular environments.