• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.11a
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• pp.1-3
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• 2010

본 논문에서는 VSB 수신기를 위한 반송파 위상 오차에 독립적인 심벌 타이밍 옵셋 추정 알고리즘을 제안하고자 한다. 심벌 타이밍 옵셋 추정에 대표적인 알고리즘인 가드너 방법은 반송파 위상 옵셋이 포함된 VSB 수신기에서는 타이밍 옵셋을 추정할 수 없다. 본 논문에서는 수신신호의 공액 곱 연산을 통하여 신호의 스펙트럼을 확장하고 반송파 위상 옵셋을 상쇄 하였고, 그 후 가드너 알고리즘을 통하여 인접 스펙트럼 간의 중복부분을 발생시켜, 타이밍 옵셋을 추정하는 방식을 연구하였다. 시뮬레이션 결과, 제안하는 알고리즘은 VSB 수신기에서 반송파 위상 오차에 영향을 받지 않고, 정확하게 타이밍 옵셋을 추정할 수 있는 것으로 나타났다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1219-1225
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• 2001

In this Paper we describe the design of synchronization algorithms for burst QPSK receiver, which are applicable to BWLL uplink. The demodulator consists of digital down converter, matched filter and synchronization circuits. For symbol timing recovery we ufo Gardner algorithm. And we use forth power method and decision directed method for carrier frequency recovery and phase recovery, respectively. For the sake of performance analysis, we compare simulation results with the board implemented by FPGA which is APEX20KE series chip for Alter. The performance results show it works quite well up to the condition that a frequency offset equal to 4.7% of symbol rate.

• Proceedings of the IEEK Conference
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• 2003.07a
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• pp.15-18
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• 2003

ATSC 방식을 사용하는 DTV 수신기는 심볼 타이밍 동기를 맞추기 위해 77.3㎲마다 존재하는 세그먼트 싱크를 이용한 방법 또는 가드너 알고리즘을 사용한다. 이 중 가드너 알고리즘을 사용하는 방법은 다중 경로 채널 환경으로 인해 타이밍 옵셋이 발생한다. DTV 수신 채널 환경이 많은 수의 다중 경로 신호를 포함하고 있기 때문에 가드너 알고리즘을 사용한 DTV 수신기는 타이밍 옵셋이 발생한다. 이 타이밍 옵셋은 샘플링 순간을 잘못된 시점으로 옮기기 때문에 등화기의 성능이 열화된다. 다중 경로 채널 환경에서 등화기의 성능을 최적화하는 샘플링 순간은 주 경로 신호의 크기가 최대가 되는 점이다. 본 논문에서는 타이밍 옵셋 보상기를 사용하여 샘플링 순간을 주 경로 신호의 최대점으로 옮겨 타이밍 옵셋을 보상하고 등화기로 입력되도록 하여 DTV 수신 성능을 개선하였다. 타이밍 옵셋 보상기는 채널 상관기, 최대점 탐색기, 타이밍 보상용 보간 필터로 구성되어 있다. 타이밍 옵셋 보상기와 등화기를 연계 실험하여 성능 향상을 분석하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.153-159
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• 2009

A CMOS frequency synthesizer for $5{\sim}6$ GHz UNII-band sub-harmonic direct-conversion receiver has been developed. For quadrature down-conversion with sub-harmonic mixing, octa-phase local oscillator (LO) signals are generated by an integer-N type phase-locked loop (PLL) frequency synthesizer. The complex timing issue of feedback divider of the PLL with large division ratio is solved by using multimodulus prescaler. Phase noise of the local oscillator signal is improved by employing the ring-type LC-tank oscillator and switching its tail current source. Implemented in a $0.18{\mu}m$ CMOS technology, the phase noise of the LO signal is lower than -80 dBc/Hz and -113 dBc/Hz at 100 kHz and 1MHz offset, respect-tively. The measured reference spur is lower than -70 dBc and the power consumption is 40 m W from a 1.8 V supply voltage.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.202-207
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• 2015

A CMOS relaxation oscillator, with high robustness over process, voltage and temperature (PVT) variations, is designed in $0.18{\mu}m$ CMOS. The proposed oscillator, consisting of full-differential charge-discharge timing circuit and switched-capacitor based voltage-to-current conversion, could be expanded to a simple open-loop frequency synthesizer (FS) with output frequency digitally tuned. Experimental results show that the proposed oscillator conducts subcarrier generation for frequency-modulated ultra-wideband (FM-UWB) transmitters with triangular amplitude distortion less than 1%, and achieves frequency deviation less than 8% under PVT and phase noise of -112 dBc/Hz at 1 MHz offset frequency. Under oscillation frequency of 10.5 MHz, the presented design has the relative FS error less than 2% for subcarrier generation and the power dissipation of 0.6 mW from a 1.8 V supply.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.481-487
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• 2016

A new two-line based inversion driving method is introduced for low power display-driver ICs. By inserting a timing offset between the chopper stabilization and the alternation of LCD polarity, we can reduce power consumption without noticeable degradation in the display quality. By applying the proposed scheme to 12" LCD applications, we achieved 7.5% and 27% power saving in the display-driver IC with white and black patterns, respectively.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.71-72
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• 2007

대역 제한된 DS/SS 시스템의 상관 함수는 최고 값이 나타나는 시점과 함께 이른 또는 늦은 상관시간 옵셋 영역에서 극소 또는 극대로 나타나는 시점을 특징점으로 갖는다. 이 가운데 이른 상관시간옵셋 영역의 상관 함수는 다중경로 신호에 의해 덜 왜곡되기 때문에 이 영역의 상관 함수를 이용해 부호 동기를 추적하여 유지할 수 있다면 EL-DLL (delay lock loop with early minus late discriminator) 보다 추적편이를 줄일 수 있다. 본 논문에 이런 특성을 이용하는 추적편이 완화 기법을 제안하고, 모의실험을 통해 성능을 알아본다.

• Korean Journal of Geomatics
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• v.4 no.2
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• pp.47-52
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• 2004

We can process and compute the position, velocity and time by satellite signals of GPS. The signals are used to compute positioning of three dimensions and timing offset of the receiver clock when we can track the tour satellite signals at least. One of the specified aims is to use less expensive single frequency code/carrier phase GPS receivers, which are typically around half the price of dual frequency receivers. In the study, the author analyzed the accuracy and applicability of frequence linear combination using triangulation points evaluated distance limitation.

• Korean Journal of Poultry Science
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• v.7 no.1
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• pp.13-22
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• 1980

On the Chicago Meracntile Exchange, individuals and firms buy and sell contracts for specified amounts of products that are to be delivered at a time period in the future at a price arrived at through openly competitive bidding. The transfer of ownership of these delivery promises takes place in a particular trading pit, for each commodity, on the floor of the Exchange. Trades are officially made by qualified members of the Exchange who act as brokers for their customers. For his services, the broker is paid a nominal round- turn commission fee by the customer. Although each commodity contract carefully describes the particular standards that product must meet in order to be a acceptable for delivery, actually fewer than three percent of the contracts traded are consummated by delivery. For the most part, contract obligations ions art offset, and thereby liquids. before the termination of the delivery month. The trader liquidates his position in the market after analyzing price trends, his timing, and his calculated price objectives. (omitted)

• Journal of Advanced Navigation Technology
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• v.7 no.1
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• pp.6-13
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• 2003

In this paper, a non-coherent code tracking loop is designed for 3GPP HSDPA MODEM and its performance is analyzed in terms of steady-state jitter variance and transient response characteristics. Analytical closed-form formula for steady-state jitter variance is first derived for AWGN environments as a function of pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. Also obtained is the transient response characteristic of a tracking loop. Finally, the performance of the designed tracking loop is confirmed by computer simulations.