• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.10 no.1
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• pp.99-108
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• 1999

In this paper, we propose $\pi$/4 QPSK scheme with block modulation algorithm, which can reduce preamble in order to transmit ATM cell efficiently in the uplink channel of LMDS, and also designed a new carrier recovery circuit which can improve carrier synchronization performance of block demodulation algorithm. The $\pi$/4 QPSK scheme employing the proposed block modulation algorithm achieved efficient frame transmission by making use of a few preamble when carrier synchronization, symbol timing synchronization and slot timing synchronization were performed by burst data of ATM cell in LMDS environment. For performance evaluation of the proposed method, a simulation analyzing the variation of carrier synchronization, symbol timing synchronization and slot timing synchronization using LMDS environment and burst mode condition was executed. In the simulation, the proposed method showed a good performance even though the reduced preamble as a few aspossible when carrier synchronization, symbol timing synchronization and slot timing synchronization is performed.

• Journal of the Korean Society of Industry Convergence
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• v.17 no.4
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• pp.234-244
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• 2014

Recently it has been focused that the automobile engine has developed in a strong upward tendency for the use of the high viscosity and poorer quality fuels in achieving the high performance, fuel economy, and emission reduction. Therefore it is not easy to solve the problems between low specific fuel consumption and exhaust emission control at motor cars. In this study, it is designed and used the engine test bed which is installed with turbocharger and intercooler. In addition to equipped using CRDI by controlling injection timing with mapping modulator, it has been tested and analyzed the engine performance, combustion characteristics, and exhaust emission as operating parameters, and they were engine speeds(rpm), injection timing(bTDC), and engine load(%). From the result of an experimental analysis, peak cylinder pressure and the rate of pressure rise were increased, and the location of it was closer toward top dead center according to the increasing of engine speed and load, and with advancing injection timing. The combustion characteristics are effected by fuel injection timing due to be enhanced the mass burned fraction. Using the engine dynamometer for analyzing the engine performance, the engine torque and power have been enhanced according to advancing the fuel injection timing. In analyzing of exhaust emission, there has been a trade-off between PM and NOx with increasing of engine speed and load, and with advanced injection timing. The experimental data are shown that the formation of NOx has increased and PM, vice versa.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.7
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• pp.501-508
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• 2004

In this paper, a coordinated scheduling algorithm is proposed to reduce end-to-end delay in distributed control of systems. For the algorithm, the analysis of practical end-to-end delay in the worst case is performed priory with considering implementation of the systems. The end-to-end delay is composed of the delay caused by multi-task scheduling of operating systems, the delay caused by network communications, and the delay caused by asynchronous timing between operating systems and network communications. Through some simulation tests based on CAN(Controller Area Network), the proposed worst case end-to-end delay analysis is validated. Through the simulation tests, it is also shown that a real-time distributed control system designed to existing worst case delay cannot guarantee end-to-end time constraints. With the analysis, a coordinated scheduling algorithm is proposed here. The coordinated scheduling algorithm is focused on the reduction of the delay caused by asynchronous timing between operating systems and network communications. Online deadline assignment strategy is proposed for the scheduling. The performance enhancement of the distributed control systems by the scheduling algorithm is shown through simulation tests.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.15 no.5
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• pp.47-57
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• 2005

For economic reasons, even though there are some security problems, the commands of re-initializing and writing patch code are widely used in smart cards. The current software tester has difficulty in detecting these trapdoor commands because trapdoors are not published and programmed sophisticatedly. Up to now the effective way to detect them is to completely reveal and analyze the entire code of the COS with applications such as the ITSEC. It is, however, a very time-consuming and expensive processes. We propose the new detecting approach of trapdoors in smart cards using timing and power analysis. With our experiments, this paper shows that the proposed approach is more practical than the current methods.

• The KIPS Transactions:PartD
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• v.13D no.3 s.106
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• pp.399-404
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• 2006

A real-time system is used for various systems from small embedded systems to distributed enterprise systems. Because it has a characteristic that provides a service on time, developers should make efforts to keep this property about time when developing real-time applications. As the result of research about real-time system indicates, TMO model supports various functions for time processing according to the real-time concept. And it guarantees response time which developers defined. So developers need a point of reference to define deadline and check the correctness of time. This paper proposes an improved PS-Block as an infrastructure of analysis tools for TMO to present a point of reference. There is a problem that the existing PS-Block has overhead caused by a policy making duplicated blocks. As such, this paper implements a PS-Block Timing Model to reduce the overhead due to block duplication, and defines a base class for searching in PS-Block. The PS-Block Timing Model, using an improved PS-Block structure, offers a point of reference of deadline and an infrastructure of execution time analysis according to the PS-Block configuration policy. Therefore, TMO developers can easily verify deadline of real-time methods, and improve reliability, and reduce development terms.

• Korean Journal of Applied Biomechanics
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• v.16 no.3
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• pp.9-18
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• 2006

These studies show that I applied to functional insole (a specific S company) for minimizing shocks and sprain people's ankle arising from running. How to an effect on human body which studied a kinematics and kinetics from 10 college students during experiments. This study imposes several conditions by barefoot, normal running shoes and put functional insole shoes ran under average $2.0{\pm}0.24$ meter per second by motion analysis, ground reaction force and electromyography that used to specific A company. First of all, Motion analysis was caused by Achilles tendon angle, Angle of the lower leg, Angle of the knee, Initial sole angle and Barefoot angle. Second, Contact time, Vertical impact force peak timing, Vertical active force and Active force timing, and Maximum loading rate under impulse of first 20 percent and Value of total impulse caused Ground reaction force. Third. The tendon fo Quadriceps femoris, Biceps femoris, Tibialis anterior and gastronemius medials caused. electromyography. 1. Ground reaction force also showed that statically approximates other results from impact peak timing (p.001), Maximum loading rate(p<.001), Maximum loading rate timing (p<.001) and impulse of first 20 percent (p<.001). 2 Electromyography showed that averagely was distinguished from other factors, and did not show about that. Above experiment values known that there was statically difference between Motion analysis and Ground reaction force under absorbing of the functional insole shoes which was not have an effect on our body for kinetics and kinematics.

• Journal of Energy Engineering
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• v.27 no.2
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• pp.49-54
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• 2018

The common rail diesel engine used in this study is a remanufactured waste engine. The fuel injection timing of the waste engine is set to be suitable for the operating conditions of the vehicle. However, the engine of a generator is operated at a constant speed and mainly at partial load. Therefore, it is necessary to change the fuel injection timing suitable for the power generation engine, and the cost and the time required for such change must be minimized as much as possible. As a result of the analysis, it was confirmed that the fuel efficiency improves according to the fuel injection timing suitable for the engine for the generator, thereby increasing the performance and fuel efficiency.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.391-393
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• 2004

For performance and stability of a synchronized system, we need an efficient Clock Tree Synthesis(CTS) methodology to design clock distribution networks. In a system-on-a-chip(SOC) design environment, CTS effectively distributes clock signals from clock sources to synchronized points on layout design. In this paper, we suggest the pre-layout analysis of the clock network including gated clock, multiple clock, and test mode CTS optimization. This analysis can help to avoid design failure with potential CTS problems from logic designers and supply layout constraints so as to get an optimal clock distribution network. Our new design flow including pre-layout CTS analysis and structural violation checking also contributes to reduce design time significantly.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.4
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• pp.21-29
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• 1998

As silicon geometry shrinks into deep submicron and the operating speed icreases, higher accuracy is required in the analysis of the propagation delays of the gates and interconnects in an ASIC. In this paper, the driving characteristics of a CMOS gate is represented by a gatedriver model, consisting of a linear resistor $R_{dr}$ and an independent ramp voltage source $V_{dr}$ . We drivered $R_{dr}$ and $V_{dr}$ as the functions of the timing data representing gate driving capability and an effective capacitance $C_{eff}$ reflecting resistance shielding effect by interconnet circuits. Through iterative applications of these equations and AWE algorithm, $R_{dr}$ , $V_{dr}$ and $C_{eff}$ are comuted simulataneously. then, the gate delay is decided by $C_{eff}$ and the interconnect circuit delay is determined by $R_{dr}$ and $V_{dr}$ . this process has been implemented as an ASIC timing analysis program written in C language and four real circuits were analyzed. In all cases, we found less than 5% of errors for both of gate andinterconnect circuit delays with a speedup factor ranging from a few tens to a few hundreds, compared to SPICE.SPICE.