• Journal of Fashion Business
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• v.25 no.5
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• pp.57-72
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• 2021

With the growing importance of CSR, more fashion brands have actively engaged in CSR activities, and consumers' perception of their motives has become a critical issue. This study investigates the influence of perceived CSR motives on fashion consumers' perceived sincerity, trust, and behavioral intentions. In addition, the effect of 'CSR timing' and 'information source' on these variables was examined. In a 2×2 between- subjects design with scenarios, 515 adult consumers responded to an online survey questionnaire. The study identified three CSR motives: value-driven motive, instrumental motive, and strategic motive. The SEM results showed that the value-driven and instrumental motives influenced trust and behavioral intentions. In particular, perceived sincerity mediates value-driven motive and trust. A comparison of latent means revealed the effect of CSR timing on value-driven and strategic motives, trust, sincerity, and behavioral intentions. This study provides an insight into the relationship between consumers' perception of CSR motives and their reactions, and the importance of CSR timing.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.57-64
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• 2019

In this paper, an efficient prediction-based parallel simulation method using spatially partial simulation strategy is proposed for improving both the performance of the event-driven gate-level timing simulation and the debugging efficiency. The proposed method quickly generates the prediction data on-the-fly, but still accurately for the input values and output values of parallel event-driven local simulations by applying the strategy to the simulation at the higher abstraction level. For those six designs which had used for the performance evaluation of the proposed strategy, our method had shown about 3.7x improvement over the most general sequential event-driven gate-level timing simulation, 9.7x improvement over the commercial multi-core based parallel event-driven gate-level timing simulation, and 2.7x improvement over the best of previous prediction-based parallel simulation results, on average.

• Proceedings of the Korean Information Science Society Conference
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• 2007.10c
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• pp.375-379
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• 2007

고성능 VLSI 설계 시 배치 후를 포함한 전체적인 설계 과정이 완성되기 전까지는 물리적인 정확한 설계의 특성은 배치 단계에서는 알기 어렵다. 따라서 주어진 성능 (시간적 제약조건)을 만족하는, 즉, timing-driven placement (타이밍이 고려된 배치)는 1.0 미크론 이하의 초미세한 설계에서 중요하게 되었다. 타이밍을 고려한 배치는 초기 레이아웃 디자인 단계에서 타이밍 제약조건에 의해 디자인 반복을 줄인다. 하지만 대부분의 배치 단계의 디자인 모델은 배치단계에서 기하학적인 면을 고려하여 최대허용 지연시간 (Slack 이라고 부름)과 같은 물리적인 디자인 효과를 분석하기 어려운데 이것은 물리적으로 정확한 특성이 이 단계에서 알려지지 않기 때문에 당연한 결과이다. 본 논문에서는 기하적인 요소를 고려한 Slack의 재분배의 이점을 이용하여 허용 지연시간 처리의 혁신적인 방법을 제안한다. 제안된 접근법은 timing-closed 솔루션을 쉽게 찾는데 도움을 주고 이는 디자인을 반복하는 시간을 절약할 수 있게 한다.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.7
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• pp.21-28
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• 2017

Practical models for FPGA architectures which include performance- and/or density-enhancing components such as carry chains, wide function multiplexers, and memory/multiplier blocks are being applied to academic FPGA placement tools which used to rely on simple imaginary models. Previously the techniques such as pre-packing and multi-layer density analysis are proposed to remedy issues related to such practical models, and the wire length is effectively minimized during initial analytic placement. Since timing should be optimized rather than wire length, most previous work takes into account the timing constraints. However, instead of the initial analytic placement, the timing-driven techniques are mostly applied to subsequent steps such as placement legalization and iterative improvement. This paper incorporates the timing driven techniques, which check if the placement meets the timing constraints given in the standard SDC format, and minimize the detected violations, with the existing analytic placer which implements pre-packing and multi-layer density analysis. First of all, a static timing analyzer has been used to check the timing of the wire-length minimized placement results. In order to minimize the detected violations, a function to minimize the largest arrival time at end points is added to the objective function of the analytic placer. Since each clock has a different period, the function is proposed to be evaluated for each clock, and added to the objective function. Since this function can unnecessarily reduce the unviolated paths, a new function which calculates and minimizes the largest negative slack at end points is also proposed, and compared. Since the existing legalization which is non-timing driven is used before the timing analysis, any improvement on timing is entirely due to the functions added to the objective function. The experiments on twelve industrial examples show that the minimum arrival time function improves the worst negative slack by 15% on average whereas the minimum worst negative slack function improves the negative slacks by additional 6% on average.

• Proceedings of the IEEK Conference
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• 2000.09a
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• pp.565-568
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• 2000

본 논문에서는 data-driven 반향제거기 구조에서 타이밍 지터의 보상 방법을 제안한다. V.90PCM 모뎀환경에서 네트윅 클록에 동기가 되어 동작하는 사용자 터미널 모뎀이 디지털 PLL (DPLL)을 이용하여 타이밍 복원을 하면 타이밍 지터 성분이 반향제거기의 성능을 순간적으로 악화 시키게 된다. 제안된 방법은 두개의 계수세트 들로부터 타이밍 지터 발생시 필요한 계수를 디콘볼루션 알고리듬을 이용하여 FIR 필터링을 통해 구하며 발생하는 지터 성분 의 대부분을 보상 해 준다. 또한 제안 방법은 waveform driven 반향제거기에 비해 약간의 성능열화가 있지만 적은 연산량으로 타이밍 지터보상을 할 수 있는 장점이 있다.

• Journal of KIISE:Computer Systems and Theory
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• v.33 no.1_2
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• pp.92-104
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• 2006

The proposed method for a force directed global placement algorithm exploits and extends techniques from two leading placers, Kraftwerk (& KraftwerkNC) and Mongrel. It combines the strengths of KraftwerkNC, force directed global placer, and Mongrel's ripple move technique which resolves cell overlaps effectively The proposed technique uses the force spreading technique used in Kraftwerk to optimize the ripple movement. While it is resolving the cell overlap and optimizing wire length physical net constraints are considered for timing. The experimental results obtained by the proposed approach shows significant improvement on wire length as well as on timing.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.10
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• pp.1344-1348
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• 1999

This paper proposes concurrent event propagation technique for timing analysis. The technique makes it possible to find several input vectors and sensitizable paths at the same time. The concurrent event propagation technique is based on the event driven simulation and the timing analysis technique with boolean equations. The technique propagates as many events as possible at the same time while preventing propagation of boolean terms which do not sensitize paths. Since events do not propagate through false paths, the longest path which successfully propagates events to one of the primary outputs is one of the longest sensitizable paths. The technique can speed up timing analysis by unifying path sensitization and maximum delay calculation.

• The Journal of Korea Robotics Society
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• v.14 no.4
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• pp.340-347
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• 2019

Due to advances in machine intelligence and increased demands for autonomous machines, the complexity of the underlying software platform is increasing at a rapid pace, overwhelming the developers with implementation details. We attempt to ease the burden that falls onto the developers by creating a graphical programming framework we named Splash. Splash is designed to provide an effective programming abstraction for autonomous machines that require stream processing. It also enables programmers to specify genuine, end-to-end timing constraints, which the Splash framework automatically monitors for violation. By utilizing the timing constraints, Splash provides three key language semantics: timing semantics, in-order delivery semantics, and rate-controlled data-driven stream processing semantics. These three semantics together collectively serve as a conceptual tool that can hide low-level details from programmers, allowing developers to focus on the main logic of their applications. In this paper, we introduce the three-language semantics in detail and explain their function in association with Splash's language constructs. Furthermore, we present the internal workings of the Splash programming framework and validate its effectiveness via a lane keeping assist system.

• Journal of Auto-vehicle Safety Association
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• v.5 no.1
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• pp.5-10
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• 2013

This paper describes a Forward Collision Warning (FCW) system based on the radar driven fusion with camera. The objective of FCW system is to provide an appropriate alert with satisfying the evaluation scenarios of US-NCAP and a driver acceptance. For this purpose, this paper proposed a data fusion algorithm and a collision warning algorithm. The data fusion algorithm generates information of fusion target depending on the confidence of camera sensor. The collision warning algorithm calculates indexes and determines an appropriate alert-timing by using analysis results of manual driving data. The FCW system with the proposed data fusion and collision warning algorithm was investigated via scenarios of US-NCAP and a real-road driving. It is shown that the proposed FCW system can improve the accuracy of an alarm-timing and reduce the false alarm in real roads.

• Journal of the Korea Society for Simulation
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• v.4 no.2
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• pp.61-68
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• 1995

The performance of event-driven logic simulation frequently used for VLSI design verification depends on the data structures for event queues. This paper improves the existing Timing Wheel as a data structure for an event queue. In case of the use of B+ tree, an efficient node degree is also presented based on the experiment results. A new Timing Wheel index structure, which eliminates the insertion and deletion overhead of B+ tree, is proposed and analyzed.