Timing Driven Placement using Force Directed Method and Optimal Interleaving Technique

포스 디렉티드 방법과 최적 인터리빙 기법을 이용한 타이밍 드리븐 배치

  • 성영태 (동아대학교 컴퓨터공학과) ;
  • 허성우 (동아대학교 컴퓨터공학과)
  • Published : 2006.02.01

Abstract

The proposed method for a force directed global placement algorithm exploits and extends techniques from two leading placers, Kraftwerk (& KraftwerkNC) and Mongrel. It combines the strengths of KraftwerkNC, force directed global placer, and Mongrel's ripple move technique which resolves cell overlaps effectively The proposed technique uses the force spreading technique used in Kraftwerk to optimize the ripple movement. While it is resolving the cell overlap and optimizing wire length physical net constraints are considered for timing. The experimental results obtained by the proposed approach shows significant improvement on wire length as well as on timing.

본 논문에서 제안하는 기법은 기존의 첨단 배치기인 Kraftwerk (& KraftwerkNC)와 Mongrel을 개선 확장한 것으로써, 광역배치에서 셀 중첩을 효과적으로 해결하는 Mongrel의 ripple move 기법과 force directed 광역배치기인 KraftwerkNC의 강력한 성능을 결합한 것이다. 제안한 기법에서는 Mongrel의 ripple move를 최적화하기 위해 Kraftwerk에서 사용한 힘 분산(force spreading)기법을 이용한다. 셀 밀집을 개선시키고, 배선길이를 최적화하는 과정에서 타이밍을 위해 넷 제약조건들이 고려된다. 제안된 기법을 통해 얻은 실험 결과는 배선길이 뿐만 아니라 타이밍에서 향상된 결과를 보여준다.

Keywords

References

  1. D. Sylvester and K. Keutzer, 'Getting to the Bottom of Deep Subrnicron,' ICCAD, pp. 203-211, 1998
  2. P. Villarrubia, 'Important Placement Considerations for Modern VLSI Chips,' ISPD, pp. 6, 2003 https://doi.org/10.1145/640000.640004
  3. Yih-Chih Chou and YourrLong Lin, 'A performance-driven standard-cell placer based on a modified force-directed algorithm,' ISPD, pp. 24-29, 2001 https://doi.org/10.1145/369691.369722
  4. Wern-Jieh and Carl Sechen, 'Efficient and Effective Placement for Very Large Circuits,' IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, pp. 349-359, 1995
  5. M. Sarrafzadeh and M. Wang, 'NRG: Global and Detailed Placement,' Proc. of ICCAD, pp. 532-537, 1997
  6. F. Romeo, A. Sangiovanni- Vincentelli, and C. Sechen, 'Research on Simulated Annealing at Berkeley,' ICCAD, pp. 652-657, 1984
  7. C. Sechen and K. W. Lee, 'An Improved Simulated Annealing Algorithm for Row-Based Placement,' ICCAD, pp. 478-481, 1987
  8. X. Yang, M. Wang, K. Egur and M. Sarrafzadeh, 'A Snap-on Placement Tool,' ISPD, pp. 153-158, 2000. https://doi.org/10.1145/332357.332392
  9. A. E. Caldwell, A. B. Kahng, and Igor L. Markov, 'Can Recursive Bisection Alone Produce Routable ?Placements?,' DAC, pp. 477-482, 2000 https://doi.org/10.1145/337292.337549
  10. D. J. -H. Huang and A. B. Kahng, 'PartitioningBased Standard-Cell Global Placement with an Exact Objective,' ISPD, pp. 18-25, 1997
  11. M. C. Yildiz and P. H. Madden, 'Improved Cut Sequences for Partitioning Based Placement,' DAC, pp. 776-729, 2001 https://doi.org/10.1145/378239.379064
  12. Ke Zhong and S. Dutt, 'Effective Partition-Driven Placement with Simultaneous Level Processing and a Global Net Views,' ICCAD, pp. 254-259, 2000 https://doi.org/10.1109/ICCAD.2000.896482
  13. A. E. Caldwell, A. B. Kahng and I. L. Markov, 'Optimal End-Case Partitioners and Placers for Standard-Cell Layout,' ISPD, pp. 90-96, 1999 https://doi.org/10.1145/299996.300032
  14. B. W. Kernighan and S. Lin, 'An Efficient Heuristic Procedure for Partitioning Graphs,' Bell Syst. Tech. J., vol. 49 no. 2, pp. 291-307, 1970
  15. C. M. Fiduccia and R. M. Matteyses, 'A Linear Time Heuristic for Improving Network Partitions,' DAC, pp. 175-181, 1982
  16. S. Goto, 'An Efficient Algorithm for the TwoDimensional Placement Problem in Electrical Circuit Layout,' IEEE Trans. Circuits and Systems, CAS-28, pp. 12-18, 1981 https://doi.org/10.1109/TCS.1981.1084903
  17. P. N. Parakh, R. B. Brown and Karem A. Sakallah, 'Congestion Driven Quadratic Placement,' DAC, pp. 275-278, 1998 https://doi.org/10.1145/277044.277121
  18. X. Yang, B.-K. Choi, and M. Sarrafzadeh, 'Routability Driven White Space Allocation for FixedDie Standard-Cell Placement,' ISPD, pp. 42-47, 2002
  19. H. Eisenmann and F. M. Johannes, 'Generic Global Placement and Floorplanning,' DAC, pp. 269-274, 1998 https://doi.org/10.1145/277044.277119
  20. H. Etawil, S. Arebi, and A. Vannelli, 'Attractor-Repeller Approach for Global Placement,' ICCAD, pp. 20-24, 1999 https://doi.org/10.1109/ICCAD.1999.810613
  21. Maogang Wang, X. Yang, Ken Eguro, and M. Sarrafzadeh, 'Dragon2000: Placement of Industrial Circuits,' ICCAD, pp. 260-263, 2000
  22. X. Yang, B-K. Choi, and M. Sarrafzadeh, 'A Standard-Cell Placement Tool for Designs with High Row Utilization,' International Conference on Computer Design, pp. 45-49 2002 https://doi.org/10.1109/ICCD.2002.1106746
  23. Karthik Rajagopal, Tal Shaked, Yegna Parasuram, Tung Cao, Amit Chowdhary, Bill Halpin, 'Timing Driven Force Directed Placement with Physical Net Constraints,' ISPD, pp. 60-66, 2003 https://doi.org/10.1145/640000.640016
  24. S. Hur and J Lillis, 'Mongrel: Hybrid Techniques for Standard Cell Placement,' ICCAD, pp. 165-170, 2000 https://doi.org/10.1109/ICCAD.2000.896468
  25. www.cbl.ncsu.edu/benchmarks/layoutsynth92/