• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.1
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• pp.22-28
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• 2009

This paper presents a fast received signal strength indicator (RSSI) circuit for wireless communication application. The proposed circuit is developed using power detectors and an analog-to-digital converter to achieve a fast settling time. The power detector is consisted of a novel logarithmic variable gain amplifier (VGA), a peak detector, and a comparator in a closed loop. The VGA achieved a wide logarithmic gain range in a closed loop form for stable operation. For the peak detector, a fast settling time and small ripple are obtained using the orthogonal characteristics of quadrature signals. In $0.18-{\mu}m$ CMOS process, the RSSI value settles down in $20{\mu}s$ with power consumption of 20 mW, and the maximum ripple of the RSSI is 30 mV. The proposed RSSI circuit is fabricated with a personal handy-phone system transceiver. The active area is $0.8{\times}0.2\;mm^2$.

• Journal of Digital Convergence
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• v.14 no.7
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• pp.193-200
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• 2016

Research and development of energy self-consumption introducing photovoltaic and energy storage system at home is very active. This system can manage the home energy in which it charges the electricity generated during the day and uses it during high electricity bills. However, it not yet made up the residential real-time pricing in Korea but it can reduce electricity usage to a certain target on the progressive. In order to introduce the home photovoltaic, it requires PCS(Power Conditioning System). This converts the direct current into alternating current by the electricity generated and used to perform charging and discharging of the energy storage system. The market for self-consumption smart home system is currently increasing because the interests of the general public about solar power, energy storage systems increased. The result of this study is installed on the room environment and the effect was analyzed on the assumption of real-time pricing.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.11
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• pp.9-16
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• 2005

This paper proposes a programmable PLL (phase locked loop) based clock generator supporting a wide-range-frequency input and output for high performance and low power SoC with multiple clock frequencies domains. The propose system reduces the locking time and obtains a wide range operation frequency by using a dual-charge pumps scheme. For low power operation of a chip, the locking processing circuits of the proposed PLL doesn't be working in the standby mode but the locking data are retained by the DAC. Also, a tracking ADC is designed for the fast relocking operation after stand-by mode exit. The programmable output frequency selection's circuit are designed for supporting a optimized DFS operation according to job tasks. The proposed PLL-based clock system has a relock time range of $0.85{\mu}sec{\sim}1.3{\mu}sec$($24\~26$cycle) with 2.3V power supply, which is fabricated on $0.35{\mu}m$ CMOS Process. At power-down mode, PLL power saves more than $95\%$ of locking mode. Also, the PLL using programmable divider has a wide locking range ($81MHz\~556MHz$) for various clock domains on a multiple IPs system.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.3
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• pp.207-217
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• 2010

Recently, the use of DC power increased due to the increased use of digital load. Power factor of input current decrease and input current harmonics increase, and conversion loss which is occurred in the AC / DC converter is a problem to provide the proper DC voltage to the device equipped with an internal AC / DC converter. Hybrid system supplies the AC power and DC power to AC load (motor load and the transformer load) and DC loads (computers, TV, LED fluorescent light) at the same time it supplies the renewable energy and utility energy taken power from Utility to user for improving the efficiency and renewable energy improvements in ease of use. This paper studies DC characteristics of traditional AC load for Hybrid distributions.

• The KIPS Transactions:PartA
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• v.11A no.2
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• pp.195-202
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• 2004

This paper introduces the design or parallel Pipeline high-speed analog-to-digital converter(ADC) for the high-resolution video applications which require very precise sampling. The overall architecture of the ADC consists of 4-channel parallel time-interleaved 10-bit pipeline ADC structure a]lowing 200MSample/s sampling speed which corresponds to 4-times improvement in sampling speed per channel. Key building blocks are composed of the front-end sample-and-hold amplifier(SHA), the dynamic comparator and the 2-stage full differential operational amplifier. The 1-bit DAC, comparator and gain-2 amplifier are used internally in each stage and they were integrated into single switched capacitor architecture allowing high speed operation as well as low power consumption. In this work, the gain of operational amplifier was enhanced significantly using negative resistance element. In the ADC, a delay line Is designed for each stage using D-flip flops to align the bit signals and minimize the timing error in the conversion. The converter has the power dissipation of 280㎽ at 3.3V power supply. Measured performance includes DNL and INL of +0.7/-0.6LSB, +0.9/-0.3LSB.

• Journal of Advanced Navigation Technology
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• v.16 no.2
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• pp.351-359
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• 2012

This paper deals with the design and development of the remote control and measurement systems using CDMA(Code Division Multiple Access) data modem. We propose a bi-directional data communication link without the public IP address in CDMA modem device by the TCP/IP packet and SMS(Short Message Service) communication. The remote control and measurement systems are implemented by a Telit WM-800 modem as DCE(Data Communication Equipment), and Atmel AT89C51 microcontroller as DTE(Data Terminal Equipment). The user application software for the control and measurement system user, and the firmware software of device drivers for peripherals such as a digital input/output device, AD/DAC(Analog to Digital/Digital to Analog Converter), LCD, and temperature/humidity sensor are written in Microsoft C and Keil C language respectively for further various applications. The experimental result of the proposed control and measurement systems implemented in this paper is evaluated via real-time experiments, which works well as designed.

• Journal of Power Electronics
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• v.15 no.1
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• pp.190-201
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• 2015

This paper uses the switching function approach to present a simple state model of the Vienna-type rectifier. The approach introduces the relationship between the DC-link neutral point voltage and the AC side phase currents. A novel direct power control (DPC) strategy, which is based on the sliding mode control (SMC) for Vienna I rectifiers, is developed using the proposed power model in the stationary ${\alpha}-{\beta}$ reference frames. The SMC-based DPC methodology directly regulates instantaneous active and reactive powers without transforming to a synchronous rotating coordinate reference frame or a tracking phase angle of grid voltage. Moreover, the required rectifier control voltages are directly calculated by utilizing the non-linear SMC scheme. Theoretically, active and reactive power flows are controlled without ripple or cross coupling. Furthermore, the fixed-switching frequency is obtained by employing the simplified space vector modulation (SVM). SVM solves the complicated designing problem of the AC harmonic filter. The simplified SVM is based on the simplification of the space vector diagram of a three-level converter into that of a two-level converter. The dwelling time calculation and switching sequence selection are easily implemented like those in the conventional two-level rectifier. Replacing the current control loops with power control loops simplifies the system design and enhances the transient performance. The simulation models in MATLAB/Simulink and the digital signal processor-controlled 1.5 kW Vienna-type rectifier are used to verify the fast responses and robustness of the proposed control scheme.

• Journal of IKEEE
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• v.16 no.1
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• pp.28-33
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• 2012

Recently, with mobile devices increasing, as a variety of multimedia functions are needed, battery life is decreased. Accordingly the methods for extending the battery life has been proposed. In order to implement these methods, we have to know exactly the status of the battery, so we need a high resolution analog to digital converter(ADC). In case of the existing integrating sigma-delta ADC, it have not convert reset-time conversion cycle to function of resolution. Because of this reason, all digital values corresponding to the all number of bits will not be able to be expressed. To compensated this drawback, this paper propose that all digital values corresponding to the number of bits can be expressed without having to convert reset-time additional conversion cycle to function of resolution by using a up-down counter. The proposed circuit achieves improved SNDR compared to conventional converters simulation result. Also, this was designed for low power suitable for battery management systems and fabricated in 0.35um process.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.2
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• pp.138-147
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• 2005

This paper presents a SPMSM(Surface-mounted Permanent Magnet Synchronous Motor) servo drive system using high performance TMS320F2812 DSP for the industrial application. The DSP(Digital Signal Processor) Controller enables an enhanced real time algorithm and cost-effective design intelligent for only exclusively motor drives which can be yield enhanced operation, fewer system components, lower control system cost, increased efficiency and high performance. The suggested system contain speed and current sensing circuits, SVPWM(Space Vector Pulse Width Modulation) and I/O interface circuit. The developed servo drive control system showns a good response characteristics results and high performance features in general purposed 400[w] machine. This system can achieve cost reduction and size minimization of controllers.

• ETRI Journal
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• v.33 no.6
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• pp.897-903
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• 2011

A hybrid ${\Delta}{\Sigma}$ modulator for audio applications is presented in this paper. The pulse generator for digital-to-analog converter alleviates the requirement of the external clock jitter and calibrates the coefficient variation due to a process shift and temperature changes. The input resistor network in the first integrator offers a gain control function in a dB-linear fashion. Also, careful chopper stabilization implementation using return-to-zero scheme in the first continuous-time integrator minimizes both the influence of flicker noise and inflow noise due to chopping. The chip is implemented in a 0.13 ${\mu}m$ CMOS technology (I/O devices) and occupies an active area of 0.37 $mm^2$. The ${\Delta}{\Sigma}$ modulator achieves a dynamic range (A-weighted) of 97.8 dB and a peak signal-to-noise-plus-distortion ratio of 90.0 dB over an audio bandwidth of 20 kHz with a 4.4 mW power consumption from 3.3 V. Also, the gain of the modulator is controlled from -9.5 dB to 8.5 dB, and the performance of the modulator is maintained up to 5 nsRMS external clock jitter.