• Title/Summary/Keyword: Time-Space Cryptography

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Secure Routing with Time-Space Cryptography for Mobile Ad-Hoc Networks (이동 애드혹 망을 위한 시공간 방식의 보안 라우팅 프로토콜)

  • Joe, In-Whee
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.32 no.1B
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    • pp.11-16
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    • 2007
  • This paper describes the design and performance of a secure routing protocol with time-space cryptography for mobile ad-hoc networks. The proposed time-space scheme works in the time domain for key distribution between source and destination as well as in the space domain for intrusion detection along the route between them. For data authentication, it relies on the symmetric key cryptography due to high efficiency and a secret key is distributed using a time difference from the source to the destination. Also, a one-way hash chain is formed on a hop-by-hop basis to prevent a compromised node or an intruder from manipulating the routing information. In order to evaluate the performance of our routing protocol, we compare it with the existing AODV protocol by simulation under the same conditions. The proposed protocol has been validated using the ns-2 network simulator with wireless and mobility extensions.

Efficient Semi-systolic Montgomery multiplier over GF(2m)

  • Keewon, Kim
    • Journal of the Korea Society of Computer and Information
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    • v.28 no.2
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    • pp.69-75
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    • 2023
  • Finite field arithmetic operations play an important role in a variety of applications, including modern cryptography and error correction codes. In this paper, we propose an efficient multiplication algorithm over finite fields using the Montgomery multiplication algorithm. Existing multipliers can be implemented using AND and XOR gates, but in order to reduce time and space complexity, we propose an algorithm using NAND and NOR gates. Also, based on the proposed algorithm, an efficient semi-systolic finite field multiplier with low space and low latency is proposed. The proposed multiplier has a lower area-time complexity than the existing multipliers. Compared to existing structures, the proposed multiplier over finite fields reduces space-time complexity by about 71%, 66%, and 33% compared to the multipliers of Chiou et al., Huang et al., and Kim-Jeon. As a result, our multiplier is proper for VLSI and can be successfully implemented as an essential module for various applications.

Quasi-Orthogonal Space-Time Block Codes Designs Based on Jacket Transform

  • Song, Wei;Lee, Moon-Ho;Matalgah, Mustafa M.;Guo, Ying
    • Journal of Communications and Networks
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    • v.12 no.3
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    • pp.240-245
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    • 2010
  • Jacket matrices, motivated by the complex Hadamard matrix, have played important roles in signal processing, communications, image compression, cryptography, etc. In this paper, we suggest a novel approach to design a simple class of space-time block codes (STBCs) to reduce its peak-to-average power ratio. The proposed code provides coding gain due to the characteristics of the complex Hadamard matrix, which is a special case of Jacket matrices. Also, it can achieve full rate and full diversity with the simple decoding. Simulations show the good performance of the proposed codes in terms of symbol error rate. For generality, a kind of quasi-orthogonal STBC may be similarly designed with the improved performance.

Low-latency Montgomery AB2 Multiplier Using Redundant Representation Over GF(2m)) (GF(2m) 상의 여분 표현을 이용한 낮은 지연시간의 몽고메리 AB2 곱셈기)

  • Kim, Tai Wan;Kim, Kee-Won
    • IEMEK Journal of Embedded Systems and Applications
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    • v.12 no.1
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    • pp.11-18
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    • 2017
  • Finite field arithmetic has been extensively used in error correcting codes and cryptography. Low-complexity and high-speed designs for finite field arithmetic are needed to meet the demands of wider bandwidth, better security and higher portability for personal communication device. In particular, cryptosystems in GF($2^m$) usually require computing exponentiation, division, and multiplicative inverse, which are very costly operations. These operations can be performed by computing modular AB multiplications or modular $AB^2$ multiplications. To compute these time-consuming operations, using $AB^2$ multiplications is more efficient than AB multiplications. Thus, there are needs for an efficient $AB^2$ multiplier architecture. In this paper, we propose a low latency Montgomery $AB^2$ multiplier using redundant representation over GF($2^m$). The proposed $AB^2$ multiplier has less space and time complexities compared to related multipliers. As compared to the corresponding existing structures, the proposed $AB^2$ multiplier saves at least 18% area, 50% time, and 59% area-time (AT) complexity. Accordingly, it is well suited for VLSI implementation and can be easily applied as a basic component for computing complex operations over finite field, such as exponentiation, division, and multiplicative inverse.

Efficiency Tests Results and New Perspectives for Secure Telecommand Authentication in Space Missions: Case-Study of the European Space Agency

  • Chiaraluce, Franco;Gambi, Ennio;Spinsante, Susanna
    • ETRI Journal
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    • v.27 no.4
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    • pp.394-404
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    • 2005
  • We discuss some typical procedures to measure the efficiency of telecommand authentication systems in space missions. As a case-study, the Packet Telecommand Standard used by the European Space Agency is considered. It is shown that, although acceptable under well consolidated evaluation suites, the standard presents some flaws particularly in regard to the randomness level of the pre-signature. For this reason, some possible changes are proposed and evaluated that should be able to improve performance, even reducing the on-board elaboration time.

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Analysis of Latency and Computation Cost for AES-based Whitebox Cryptography Technique (AES 기반 화이트박스 암호 기법의 지연 시간과 연산량 분석)

  • Lee, Jin-min;Kim, So-yeon;Lee, Il-Gu
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2022.05a
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    • pp.115-117
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    • 2022
  • Whitebox encryption technique is a method of preventing exposure of encryption keys by mixing encryption key information with a software-based encryption algorithm. Whitebox encryption technique is attracting attention as a technology that replaces conventional hardware-based security encryption techniques by making it difficult to infer confidential data and keys by accessing memory with unauthorized reverse engineering analysis. However, in the encryption and decryption process, a large lookup table is used to hide computational results and encryption keys, resulting in a problem of slow encryption and increased memory size. In particular, it is difficult to apply whitebox cryptography to low-cost, low-power, and light-weight Internet of Things products due to limited memory space and battery capacity. In addition, in a network environment that requires real-time service support, the response delay time increases due to the encryption/decryption speed of the whitebox encryption, resulting in deterioration of communication efficiency. Therefore, in this paper, we analyze whether the AES-based whitebox(WBC-AES) proposed by S.Chow can satisfy the speed and memory requirements based on the experimental results.

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Elliptic Curve Cryptography Coprocessors Using Variable Length Finite Field Arithmetic Unit (크기 가변 유한체 연산기를 이용한 타원곡선 암호 프로세서)

  • Lee Dong-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.42 no.1
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    • pp.57-67
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    • 2005
  • Fast scalar multiplication of points on elliptic curve is important for elliptic curve cryptography applications. In order to vary field sizes depending on security situations, the cryptography coprocessors should support variable length finite field arithmetic units. To determine the effective variable length finite field arithmetic architecture, two well-known curve scalar multiplication algorithms were implemented on FPGA. The affine coordinates algorithm must use a hardware division unit, but the projective coordinates algorithm only uses a fast multiplication unit. The former algorithm needs the division hardware. The latter only requires a multiplication hardware, but it need more space to store intermediate results. To make the division unit versatile, we need to add a feedback signal line at every bit position. We proposed a method to mitigate this problem. For multiplication in projective coordinates implementation, we use a widely used digit serial multiplication hardware, which is simpler to be made versatile. We experimented with our implemented ECC coprocessors using variable length finite field arithmetic unit which has the maximum field size 256. On the clock speed 40 MHz, the scalar multiplication time is 6.0 msec for affine implementation while it is 1.15 msec for projective implementation. As a result of the study, we found that the projective coordinates algorithm which does not use the division hardware was faster than the affine coordinate algorithm. In addition, the memory implementation effectiveness relative to logic implementation will have a large influence on the implementation space requirements of the two algorithms.

A Novel Approach for Integrating Security in Business Rules Modeling Using Agents and an Encryption Algorithm

  • Houari, Nawal Sad;Taghezout, Noria
    • Journal of Information Processing Systems
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    • v.12 no.4
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    • pp.688-710
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    • 2016
  • Our approach permits to capitalize the expert's knowledge as business rules by using an agent-based platform. The objective of our approach is to allow experts to manage the daily evolutions of business domains without having to use a technician, and to allow them to be implied, and to participate in the development of the application to accomplish the daily tasks of their work. Therefore, the manipulation of an expert's knowledge generates the need for information security and other associated technologies. The notion of cryptography has emerged as a basic concept in business rules modeling. The purpose of this paper is to present a cryptographic algorithm based approach to integrate the security aspect in business rules modeling. We propose integrating an agent-based approach in the framework. This solution utilizes a security agent with domain ontology. This agent applies an encryption/decryption algorithm to allow for the confidentiality, authenticity, and integrity of the most important rules. To increase the security of these rules, we used hybrid cryptography in order to take advantage of symmetric and asymmetric algorithms. We performed some experiments to find the best encryption algorithm, which provides improvement in terms of response time, space memory, and security.

Quantum rebound attacks on reduced-round ARIA-based hash functions

  • Seungjun Baek;Jongsung Kim
    • ETRI Journal
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    • v.45 no.3
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    • pp.365-378
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    • 2023
  • ARIA is a block cipher proposed by Kwon et al. at ICISC 2003 that is widely used as the national standard block cipher in the Republic of Korea. Herein, we identify some flaws in the quantum rebound attack on seven-round ARIA-DM proposed by Dou et al. and reveal that the limit of this attack is up to five rounds. Our revised attack applies to not only ARIA-DM but also ARIA-MMO and ARIA-MP among the PGV models, and it is valid for all ARIA key lengths. Furthermore, we present dedicated quantum rebound attacks on seven-round ARIA-Hirose and ARIA-MJH for the first time. These attacks are only valid for the 256-bit key length of ARIA because they are constructed using the degrees of freedom in the key schedule. All our attacks are faster than the generic quantum attack in the cost metric of the time-space tradeoff.

Design of LSB Multiplier using Cellular Automata (셀룰러 오토마타를 이용한 LSB 곱셈기 설계)

  • 하경주;구교민
    • Journal of Korea Society of Industrial Information Systems
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    • v.7 no.3
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    • pp.1-8
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    • 2002
  • Modular Multiplication in Galois Field GF(2/sup m/) is a basic operation for many applications, particularly for public key cryptography. This paper presents a new architecture that can process modular multiplication on GF(2/sup m/) per m clock cycles using a cellular automata. Proposed architecture is more efficient in terms of the space and time than that of systolic array. Furthermore it can be efficiently used for the hardware design for exponentiation computation.

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