• Journal of the Korean Institute of Telematics and Electronics
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• v.14 no.5
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• pp.1-6
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• 1977

When the input of synchronizer which is used for the purpose of synchronizing the master clock of computer with the interrupt system, a sort of random variable device, is gated with asynchronous intersection of the fall time of the master clock and the risetime oi the interrupt request, synchronizer is drived in Metastable region. This paper is presented circuit analysis of Metastable phenomena and analysis for transient process from metastable point to stable state, and also realities the collect logic with Inverter and open collector methods with a view to improving logic failure caused by the mishappen phenomena.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.15 no.2
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• pp.44-50
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• 2006

A driver's feelings of transmission serve as a basis to judge not only the transmission but also the entire automobile that he or she drives. The importance of transmission feelings is increasing daily because of driver's desire for increased torque and other improved functions. In order to accommodate such desire of drivers, new friction materials have been developed. The study in this report compared the affects of such materials and the force for transmission theoretically and empirically. By doing so, the study attempted to establish basic references for computation of capacity and other factors to be determined at the time of design of synchronizer system.

• Journal of Advanced Navigation Technology
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• v.18 no.5
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• pp.476-482
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• 2014

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. IEEE 802.15.4 LR-WPAN system using 2.45 GHz frequency band is very popular for the sensor applications. However, since LR-WPAN only supports the data rate of 250 kbps, it has a limit to be applied to various sensor networks. Therefore, we define the preamble structure which can support the data rates of 31.25 kbps, 62.5 kbps, 125 kbps, and present the low-complexity hardware architecture for time synchronizer based on double-correlation algorithm which can resist the CFO (carrier frequency offset). Implementation results show that the proposed time synchronizer include the logic slice of 18.36 K and four DSP48s, which are reduced at the rate of 79.1% and 99.4%, respectively, compared with existing architecture.

• Proceedings of the KSRS Conference
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• 2007.10a
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• pp.522-525
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• 2007

Frame Synchronization is applied to not only digital data transmission for data synchronization between transmitter and receiver but also data communication with satellite. When satellite image data with high resolution and mass storage is transmitted, hardware frame synchronizer for real-time processing or software frame synchronizer for post-processing is used. In case of hardware, processing with high speed is available but data loss may happen for Search of Frame Synchronization. In case of software, data loss does not happen but speed is relatively slow. In this paper, Pending Buffer concept was proposed to cope with data loss according to processing status of Frame Synchronization. Algorithm to process Frame synchronization with high speed using bit threshold search algorithm with pattern search technique and SIMD is also proposed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.11
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• pp.2401-2408
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• 1997

The measured pulse shapes provided in the given data package demonstrated pulse distortions due to laser speckle. the distorted pulse shapes were carefully analyzed, modeled, and then applied to the DTTL(Digital-data Transition Tracking Loop)[1] bit synchronizer simulator to measure the mean time delay and its delay variation performance. The result showed that the maximum mean time delay variation with the modeled data was 12.5% when window size equals 1. All the data given were located within this modeled boundary and the maximum eman time delay variation was 7% in this case. The mean time delay variation was known to be smaller by reducing the window size [2][5][6]. The mitigated delay variation was 2.5% in the modeled case and 1.4% in the data set given when the windown size equals 0.1. With the digital DTTL insteal of analog DTTL, similar results was obtained.

• 제어로봇시스템학회:학술대회논문집
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• 1991.10b
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• pp.1817-1822
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• 1991

A method of reducing overhead caused by the processor synchronization process and common memory accesses in finely grained tasks is described. We propose a scheduler which considers the preparation time during searching to minimize the redundant accesses to shared memory. Since the suggested hardware (synchronizer) determines the access order of processors and bus arbitration simultaneously by including the synchronization process into the bus arbitration process, the synchronization time vanishes. Therefore this synchronizer has no overhead caused by the processor synchronization[l]. The proposed scheduler algorithm is processed in parallel. The processes share the upper bound derived by each searching and the lower bound function is built considering the preparation time in order to eliminate as many searches as possible. An application of the proposed method to a multi-DSP system to calculate inverse dynamics for robot arms, showed that the sampling time can be twice shorter than that of the conventional one.

• The Journal of the Korea institute of electronic communication sciences
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• v.10 no.8
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• pp.883-890
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• 2015

As the semiconductor processing technology has been developing, multiple cores or NoC(network on chip) can be contained in recent chips. GALS(globally asychronous locally synchronous) clocking scheme that has multi-clock domains with different frequencies or phase differences is widely used to solve power consumption and clock skew in a large chip with a single clock. A synchronizer is needed to avoid a synchronization problem between sender and receiver in GALS. In this paper, the setup and hold time of DFF required to design the synchronizer are measured using 180nm CMOS processing parameters depending on temperature, supply voltage, and the size of inverter in DFF. The simulation results based on the bisection method in HSPICE show that the setup and hold time are proportional to temperature, however they are inversely proportional to supply voltage, and negative values are measured for the hold time.

• Journal of Advanced Navigation Technology
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• v.20 no.5
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• pp.453-461
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• 2016

Recently, with the growth of various sensor applications, the need of wireless communication systems which can support variable data rate is increasing. Therefore, advanced ZigBee (AZB) systems that support the various data rate under 250 kbps are proposed. However, the preamble structure for AZB systems causes the complexity increase of time synchronization circuits. In this paper, we propose preamble structure and time synchronization algorithm which can solve the problem of the complexity increase of time synchronization circuits. Implementation results show that the proposed time synchronizer for AZB systems include the logic slices of 6.92 k and, which are reduced at the rate of 62.3% compared with existing architecture.

• ETRI Journal
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• v.35 no.4
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• pp.706-709
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• 2013

As an alternative to the traditional pilot-aided orthogonal frequency division multiplexing (OFDM), the time-domain pseudonoise (PN)-padded OFDM provides a higher spectral efficiency. However, the carrier frequency offset (CFO) attenuates peaks of the conventional PN correlation output, which limits the CFO estimation range of the OFDM synchronizer. An improved correlation is proposed in this letter to remove the CFO-induced amplitude attenuation of correlation peaks. For a synchronizer adopting the designed correlator, a larger range of CFO acquisition is obtained through using wider correlation windows with a smaller interval between them. The proposed method of CFO acquisition is verified in a digital terrestrial multimedia broadcast receiver, in which the synchronizer is able to acquire CFOs up to ${\pm}320$ kHz in the DVB-T F1 channel. Furthermore, the acquisition range can be expanded in more favorable channels.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.12
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• pp.1345-1352
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• 2014

Bus architecture of SoC has been replaced by NoC in recent years. Noc uses the multi-clock domains to transmit and receive data between neighbor network interfaces and they have same frequency, but a phase difference because of clock skew. So a synchronizer is used for a mesochronous frequency in interconnection between network interfaces. In this paper the metastability is defined and analyzed in a D latch and a D flip-flop to search the possibilities that data can be lost in the process of sending and receiving data between interconnects when a local frequency and a transmitted frequency have a phase difference. 180nm CMOS model parameter and 1GHz are used to simulate them in HSpice. The simulation results show that the metastability happens in a latch and a flip-flop when input data change near the clock edges and there are intermediate states for a longer time as input data change closer at the clock edge. And the next stage can lose input data depending on environmental conditions such as temperature, processing variations, power supply, etc. The simulation results are very useful to design a mescochronous synchronizer for NoC.