• Title/Summary/Keyword: Time complexity

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Revolution of nuclear energy efficiency, economic complexity, air transportation and industrial improvement on environmental footprint cost: A novel dynamic simulation approach

  • Ali, Shahid;Jiang, Junfeng;Hassan, Syed Tauseef;Shah, Ashfaq Ahmad
    • Nuclear Engineering and Technology
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    • v.54 no.10
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    • pp.3682-3694
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    • 2022
  • The expansion of a country's ecological footprint generates resources for economic development. China's import bill and carbon footprint can be reduced by investing in green transportation and energy technologies. A sustainable environment depends on the cessation of climate change; the current study investigates nuclear energy efficiency, economic complexity, air transportation, and industrial improvement for reducing environmental footprint. Using data spanning the years 1983-2016, the dynamic autoregressive distributed lag simulation method has demonstrated the short- and long-term variability in the impact of regressors on the ecological footprint. The study findings revealed that economic complexity in China had been found to have a statistically significant impact on the country's ecological footprint. Moreover, the industrial improvement process is helpful for the ecological footprint in China. In the short term, air travel has a negative impact on the ecological footprint, but this effect diminishes over time. Additionally, energy innovation is negative and substantial both in the short and long run, thus demonstrating its positive role in reducing the ecological footprint. Policy implications can be extracted from a wide range of issues, including economic complexity, industrial improvement, air transportation, energy innovation, and ecological impact to achieve sustainable goals.

Chromatic Number Algorithm for Exam Scheduling Problem (시험 일정 계획 수립 문제에 관한 채색 수 알고리즘)

  • Lee, Sang-Un
    • Journal of the Korea Society of Computer and Information
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    • v.20 no.4
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    • pp.111-117
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    • 2015
  • The exam scheduling problem has been classified as nondeterministic polynomial time-complete (NP-complete) problem because of the polynomial time algorithm to obtain the exact solution has been unknown yet. Gu${\acute{e}}$ret et al. tries to obtain the solution using linear programming with $O(m^4)$ time complexity for this problem. On the other hand, this paper suggests chromatic number algorithm with O(m) time complexity. The proposed algorithm converts the original data to incompatibility matrix for modules and graph firstly. Then, this algorithm packs the minimum degree vertex (module) and not adjacent vertex to this vertex into the bin $B_i$ with color $C_i$ in order to exam within minimum time period and meet the incompatibility constraints. As a result of experiments, this algorithm reduces the $O(m^4)$ of linear programming to O(m) time complexity for exam scheduling problem, and gets the same solution with linear programming.

Credit-Based Round Robin for High Speed Networks (고속 통신망을 위한 크레딧 기반 라운드 로빈)

  • 남홍순;김대영;이형섭;이형호
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.27 no.12C
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    • pp.1207-1214
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    • 2002
  • A scheduling scheme for high speed networks requires a low time complexity to schedule packets in a packet transmission time. High speed networks support a number of connections, different rates for each connection and variable packet length. Conventional round robin algorithms have a time complexity of O(1), but their short time fairness, latency and burstiness depend on the quantum of a connection due to serving several packets for a backlogged connection once a round. To improve these properties, we propose in this paper an efficient packet scheduling scheme which is based on the credits of a connection and has a time complexity of O(1). We also analyzed its performance in terms of short time fairness, latency and burstiness. The analysis results show that the proposed scheme can improve the performance compared with traditional round robin schemes. The proposed scheme can be easily utilized in high speed packet networks.

An expanded Matrix Factorization model for real-time Web service QoS prediction

  • Hao, Jinsheng;Su, Guoping;Han, Xiaofeng;Nie, Wei
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.11
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    • pp.3913-3934
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    • 2021
  • Real-time prediction of Web service of quality (QoS) provides more convenience for web services in cloud environment, but real-time QoS prediction faces severe challenges, especially under the cold-start situation. Existing literatures of real-time QoS predicting ignore that the QoS of a user/service is related to the QoS of other users/services. For example, users/services belonging to the same group of category will have similar QoS values. All of the methods ignore the group relationship because of the complexity of the model. Based on this, we propose a real-time Matrix Factorization based Clustering model (MFC), which uses category information as a new regularization term of the loss function. Specifically, in order to meet the real-time characteristic of the real-time prediction model, and to minimize the complexity of the model, we first map the QoS values of a large number of users/services to a lower-dimensional space by the PCA method, and then use the K-means algorithm calculates user/service category information, and use the average result to obtain a stable final clustering result. Extensive experiments on real-word datasets demonstrate that MFC outperforms other state-of-the-art prediction algorithms.

Efficient Collaboration Method Between CPU and GPU for Generating All Possible Cases in Combination (조합에서 모든 경우의 수를 만들기 위한 CPU와 GPU의 효율적 협업 방법)

  • Son, Ki-Bong;Son, Min-Young;Kim, Young-Hak
    • KIPS Transactions on Computer and Communication Systems
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    • v.7 no.9
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    • pp.219-226
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    • 2018
  • One of the systematic ways to generate the number of all cases is a combination to construct a combination tree, and its time complexity is O($2^n$). A combination tree is used for various purposes such as the graph homogeneity problem, the initial model for calculating frequent item sets, and so on. However, algorithms that must search the number of all cases of a combination are difficult to use realistically due to high time complexity. Nevertheless, as the amount of data becomes large and various studies are being carried out to utilize the data, the number of cases of searching all cases is increasing. Recently, as the GPU environment becomes popular and can be easily accessed, various attempts have been made to reduce time by parallelizing algorithms having high time complexity in a serial environment. Because the method of generating the number of all cases in combination is sequential and the size of sub-task is biased, it is not suitable for parallel implementation. The efficiency of parallel algorithms can be maximized when all threads have tasks with similar size. In this paper, we propose a method to efficiently collaborate between CPU and GPU to parallelize the problem of finding the number of all cases. In order to evaluate the performance of the proposed algorithm, we analyze the time complexity in the theoretical aspect, and compare the experimental time of the proposed algorithm with other algorithms in CPU and GPU environment. Experimental results show that the proposed CPU and GPU collaboration algorithm maintains a balance between the execution time of the CPU and GPU compared to the previous algorithms, and the execution time is improved remarkable as the number of elements increases.

A New Multiuser Receiver for the Application Of Space-time Coded OFDM Systems

  • Pham, Van-Su;Le, Minh-Tuan;Mai, Linh;Lee, Jae-Young;Yoon, Gi-Wan
    • Journal of information and communication convergence engineering
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    • v.4 no.4
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    • pp.151-154
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    • 2006
  • In this work, a novel optimal multiuser detection (MUD) approach, which not only achieves the optimal maximum-likelihood (ML)-like performance but also has reasonably low computational complexity, for Space-time coded OFDM (ST-OFDM) systems is presented. In the proposed detection scheme, the signal model is firstly re-expressed into linearly equivalent one. Then, with the linearly equivalent signal model, a new jointly MUD algorithm is proposed to detect signals. The ML-like bit-error-rate (BER) performance and reasonably low complexity of the proposed detection are verified by computer simulations.

A Study of Ordering Sphere Decoder Class for Space-Time Codes

  • Pham, Van-Su;Mai, Linh;Kabir, S.M. Humayun;Yoon, Gi-Wan
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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    • 2008.05a
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    • pp.567-571
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    • 2008
  • In this paper, an overview on the ordering sphere decoder (SD) class for space-time codes (STC) will be presented. In SDs, the ordering techniques are considered as promising methods for reducing complexity by exploiting a sorted list of candidates, thus decreasing the number of tested points. First, we will present the current state of art of SD with their advantages and disadvantages. Then, the overview of simply geometrical approaches for ordering is presented to address the question to overcome the disadvantages. The computer simulation results shown that, thanks to the aid of ordering, the ordering SDs can achieve optimal bit-error-rate (BER) performance while requiring the very low complexity, which is comparable to that of linear sub-optimal decoders.

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Removal of Complexity Management in H.263 Codec for A/VDelivery Systems

  • Jalal, Ahmad;Kim, Sang-Wook
    • 한국HCI학회:학술대회논문집
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    • 2006.02a
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    • pp.931-936
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    • 2006
  • This paper presents different issues of the real-time compression algorithms without compromising the video quality in the distributed environment. The theme of this research is to manage the critical processing stages (speed, information lost, redundancy, distortion) having better encoded ratio, without the fluctuation of quantization scale by using IP configuration. In this paper, different techniques such as distortion measure with searching method cover the block phenomenon with motion estimation process while passing technique and floating measurement is configured by discrete cosine transform (DCT) to reduce computational complexity which is implemented in this video codec. While delay of bits in encoded buffer side especially in real-time state is being controlled to produce the video with high quality and maintenance a low buffering delay. Our results show the performance accuracy gain with better achievement in all the above processes in an encouraging mode.

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Serial Concatenation of Space-Time and Recursive Convolutional Codes

  • Ko, Young-Jo;Kim, Jung-Im
    • ETRI Journal
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    • v.25 no.2
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    • pp.144-147
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    • 2003
  • We propose a new serial concatenation scheme for space-time and recursive convolutional codes, in which a space-time code is used as the outer code and a single recursive convolutional code as the inner code. We discuss previously proposed serial concatenation schemes employing multiple inner codes and compare them with the new one. The proposed method and the previous one with joint decoding, both performing a combined decoding of the simultaneous output signals from multiple antennas, give a large performance gain over the separate decoding method. In decoding complexity, the new concatenation scheme has a lower complexity compared with the multiple encoding/joint decoding scheme due to the use of the single inner code. Simulation results for a communication system with two transmit and one receive antennas in a quasi-static Rayleigh fading channel show that the proposed scheme outperforms the previous schemes.

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Design of Low-Latency Architecture for AB2 Multiplication over Finite Fields GF(2m) (유한체 GF(2m)상의 낮은 지연시간의 AB2 곱셈 구조 설계)

  • Kim, Kee-Won;Lee, Won-Jin;Kim, HyunSung
    • IEMEK Journal of Embedded Systems and Applications
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    • v.7 no.2
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    • pp.79-84
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    • 2012
  • Efficient arithmetic design is essential to implement error correcting codes and cryptographic applications over finite fields. This article presents an efficient $AB^2$ multiplier in GF($2^m$) using a polynomial representation. The proposed multiplier produces the result in m clock cycles with a propagation delay of two AND gates and two XOR gates using O($2^m$) area-time complexity. The proposed multiplier is highly modular, and consists of regular blocks of AND and XOR logic gates. Especially, exponentiation, inversion, and division are more efficiently implemented by applying $AB^2$ multiplication repeatedly rather than AB multiplication. As compared to related works, the proposed multiplier has lower area-time complexity, computational delay, and execution time and is well suited to VLSI implementation.