• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.12
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• pp.39-47
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• 2010

This paper proposes a fully-utilized block-based 2D DWT architecture, which consists of four 1D DWT filters with two-channel QMF PR Lattice structure. For 100% hardware utilization, we propose a new method which processes four input values at the same time. On the contrary to the image-based 2D DWT which requires large memories, we propose a block-based 2D DWT so that we only need 2MN-3N of storages, where M and N stand for filter lengths and width of the image respectively. Furthermore, the proposed architecture processes in horizontal and vertical directions simultaneously so that it computes the DWT for an $N{\times}N$ image within a period of $N^2(1-2^{-2J})/3$. Compared to existing approaches, the proposed architecture shows 100% of hardware utilization and high throughput rate. However, the proposed architecture may suffer from the long critical path delay due to the cascaded lattices in 1D DWT filters. This problem can be mitigated by applying the pipeline technique with maximum four level. The proposed architecture has been designed with VerilogHDL and synthesized using DongbuAnam $0.18{\mu}m$ standard cell.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.1
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• pp.139-145
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• 2016

Dumbbell is the most basic topology that can be used in almost all kind of network experiment within it or just by little expansion. While Transmission Control Protocol TCP is the basic protocol that is used for the connectivity among networks and stations. TCP major and basic goal is to provide path and services to different applications for communication. For that reason TCP has to transfer a lot of data through a communication medium that cause serious congestion problem. To calculate the congestion problem, different kind of pre-cure solutions are developer which are Loss Based Variant and Delay Based Variant. While LBV keep track of the data that is going to be passed through TCP protocol, if the data packets start dropping that means congestion occurrence which notify as a symptom, TCP CUBIC use LBV for notifying the loss. Similarly the DBV work with the acknowledgment procedure that is used in when data ACK get late with respect to its set data rate time, TCP COMPOUND/VAGAS are examples of DBV. Many algorithms have been purposed to control the congestion in different TCP variants but the loss of data packets did not completely controlled. In this paper, the congestion control algorithms are implemented and corresponding results are analyzed in Dumbbell topology, it is typically used to analyze the TCP traffic flows. Fairness of throughput is evaluated for different TCP variants using network simulator (NS-2).

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.187-187
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF($2^8$) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.3
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• pp.29-38
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• 2004

In this paper, we present an efficient architecture of a versatile Reed-Solomon (RS) decoder which can be programmed to decode RS codes continuously with my message length k as well as any block length n. This unique feature eliminates the need of inserting zeros for decoding shortened RS codes. Also, the values of the parameters n and k, hence the error-correcting capability t can be altered at every codeword block. The decoder permits 3-step pipelined processing based on the modified Euclid's algorithm (MEA). Since each step can be driven by a separate clock, the decoder can operate just as 2-step pipeline processing by employing the faster clock in step 2 and/or step 3. Also, the decoder can be used even in the case that the input clock is different from the output clock. Each step is designed to have a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for variable values of the t. The operating length of the shift registers in the MEA block is shortened by one, and it can be varied according to the different values of the t. To maintain the throughput rate with less circuitry, the MEA block uses both the recursive technique and the over-clocking technique. The decoder can decodes codeword received not only in a burst mode, but also in a continuous mode. It can be used in a wide range of applications because of its versatility. The adaptive RS decoder over GF(2$^{8}$ ) having the error-correcting capability of upto 10 has been designed in VHDL, and successfully synthesized in an FPGA chip.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.13-18
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• 2016

In Long Term Evolution-Advanced (LTE-A), small cell enhancement(SCE) has been developed as a cost-effective way of supporting exponentially increasing demand of wireless data services and satisfying the user quality of service(QoS). However, there are many problems such as the transmission rate and transmission quality degradation due to the dense and irregular distribution of a large number of small cells. In this paper, we propose a clustering based interference management scheme in dense small cell network. We divide the small cells into different clusters according to the reference signal received power(RSRP) from user equipment(UE). Within a cluster, an almost blank subframe(ABS) is implemented to mitigate interference between the small cells. In addition, we apply the power control to reduce the interference between the clusters. Simulation results show that proposed scheme can improve Signal to Interference plus Noise Ratio(SINR), throughput, and spectral efficiency of small cell users. Eventually, proposed scheme can improve overall cell performance.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.101-111
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• 2008

This paper introduces a high-speed Reed-Solomon(RS) decoder, which reduces the hardware complexity, and presents an RS decoder based FEC architecture which is used for 40Gb/s optical communication systems. We introduce new pipelined degree computationless modified Euclidean(pDCME) algorithm architecture, which has high throughput and low hardware complexity. The proposed 16 channel RS FEC architecture has two 8 channel RS FEC architectures, which has 8 syndrome computation block and shared single KES block. It can reduce the hardware complexity about 30% compared to the conventional 16 channel 3-parallel FEC architecture, which is 4 syndrome computation block and shared single KES block. The proposed RS FEC architecture has been designed and implemented with the $0.18-{\mu}m$ CMOS technology in a supply voltage of 1.8 V. The result show that total number of gate is 250K and it has a data processing rate of 5.1Gb/s at a clock frequency of 400MHz. The proposed area-efficient architecture can be readily applied to the next generation FEC devices for high-speed optical communications as well as wireless communications.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.118-124
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• 2008

For forward error correction, DVB-S2, which is the digital video broadcasting forward error coding and modulation standard for satellite television, uses a system based the concatenation of BCH with LDPC inner coding. In DVB-S2 the LDPC codes are defined for 11 different code rates, which means that a DVB-S2 LDPC decoder should support multiple code rates. Seven of the 11 code rates, 3/5, 2/3, 3/4, 4/5, 5/6, 8/9, and 9/10, are regular and the rest four code rates, 1/4, 1/3, 2/5, and 1/2, are irregular. In this paper we propose a flexible decoder for the regular LDPC codes. We combined the partially parallel decoding architecture that has the advantages in the chip size, the memory efficiency, and the processing rate with Benes network to implement a DVB-S2 LDPC decoder that can support multiple code rates with a block size of 64,800 and can configure the interconnection between the variable nodes and the check nodes according to the parity-check matrix. The proposed decoder runs correctly at the frequency of 200MHz enabling 193.2Mbps decoding throughput. The area of the proposed decoder is $16.261m^2$ and the power dissipation is 198mW at a power supply voltage of 1.5V.

• The KIPS Transactions:PartC
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• v.9C no.4
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• pp.605-614
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• 2002

Amount of the web traffic web server handles are explosively increasing, which requires that the performance of the web server should be improved for the various web services. Although the analysis for the HTTP traffic with the proper tuning for the web server is essential, the research relevant to the subject are insignificant. In particular, although most of applications are implemented over HTTP 1.1 protocol, the researches mostly deal with the performance evaluation of the HTTP 1.0 protocol. Consequently, the modeling approach and the performance evaluation over HTTP 1.1 protocol have not been well formed. Therefore, basing on the HTTP 1.1 protocol supporting persistent connection, we present an analytical end-to-end tandem queueing model for web server to consider the specific hardware configuration inside web server beginning at accepting the user request until completing the service. we compare various performances between HTTP 1.0 and HTTP 1.1 under the overloading condition, and then analyze the characteristics of the HTTP traffic that include file size requested to web server, the OFF time between file transfers, the frequency of requests, and the temporal locality of requests. Presented model is verified through the comparing the server throughput according to varying requests rate with the real web server. Thereafter, we analyze the performance evaluation of the web server, according to the interrelation between TCP Listen queue size, the number of HTTP threads and the size of the network buffers.

• Journal of the Korean Recycled Construction Resources Institute
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• v.4 no.1
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• pp.81-88
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• 2009

This study has shown the tendency to enhance Sand Flux, a device of separating screening the foreign matter, for the recycling of construction waste possible to improve the quality of wet type production system meaningfully as part of research. As a result of experiment on the basic material properties, this study had a tendency to improve the quality and performance significantly in case of absolute surface dried density, 0.08mm sieve throughput, volume of clay lumps, and content of organic foreign matter. In addition, as a result of examining the quality characteristics of mortar, this study has shown the tendency that the flow and compressive strength more increased than the mortar using RS-II by utilizing RS-VI recycled sand produced finally through the device Sand Flux. As for the shrinkage properties, this study has shown the character the generation rate of crack of mortar using RS-IV recycled sand produced finally through the device Sand Flux.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.2A
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• pp.107-114
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• 2008

In wireless access systems, there has been much interest in enhancing the performance of orthogonal frequency division multiplexing OFDM) in a frequency selective fading channel. If the channel is static and is perfectly known to both the transmitter and the receiver, the water-filling technique with adaptive modulation is known to be optimal. However, for OFDM systems, this requires intensive traffic overheads for reporting channel side information on all subcarriers to the transmitter In this paper, we propose an adaptive modulation and coding scheme for bit-interleaved coded OFDM (BIC-OFDM) for downlink packet transmissions with reduced feedback information. To minimize the feedback information, we employ a rate adaptation method based on the OFDM symbol rather than on each subcarrier. To illustrate the performance gap between the optimal water-filling and the proposed scheme, we will compare cutoff rates for both schemes. It is shown that the loss is less than 2dB while the proposed scheme significantly reduces the feedback payloads. Also, the OFDM system in multiuser environment with subcarrier grouping is considered. It is shown that by exploiting multiuser diversity the throughput of the proposed scheme approaches the channel outage capacity as the number of users and the number of subcarrier groups increase.