• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2010.06a
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• pp.314-314
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• 2010

The SiC-$ZrB_2$ composites were fabricated by combining 40vol.% of Zirconium Diboride(hereafter, $ZrB_2$) powders with Silicon Carbide(hereafter, SiC) matrix. TheSiC+40vol.%$ZrB_2$ composites were manufactured through Spark Plasma Sintering(hereafter, SPS) under argon atmosphere, uniaxial pressure of 50MPa, heating rate of $100^{\circ}C$/min, sintering temperature of $1,500^{\circ}C$ and holding time of 5min. But one on/off pulse sequence(one pulse time: 2.78ms) is 10:9(hereafter, SZ10), and the other is 48:8(hereafter, SZ48). The physical and mechanical properties of the SZ12 and SZ48 were examined. Reactions between $\beta$-SiC and $ZrB_2$ were not observed via X-Ray Diffraction(hereafter, XRD) analysis. The apparent porosity of the SZ10 and SZ48 composites were 9.7455 and 12.2766%, respectively. The SZ10 composite, 593.87MPa, had higher flexural strength than the SZ48 composite, 324.78MPa, at room temperature. The electrical properties of the SiC-$ZrB_2$ composites had Positive Temperature Coefficient Resistance(hereafter, PTCR).

• Journal of the Korean Vacuum Society
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• v.8 no.1
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• pp.63-69
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• 1999

The characteristic parameters of high density plasma source (Helical Resonator) have been measured with Langmuir probe to get the plasma density electron temperature, ion current density, etc. Optical emission spectra of Si and SiCl have been analyzed in $Cl_2$$/poly-Si system to elucidate etching mechanism. In this system, the main reaction to remove silicon atoms on the surface is proceeding mostly through chemical reaction, not pure physical reaction. The emission intensity of SiCl (chemical etching product) increases much faster than Si (pure physical etching product) with increasing the concentration of impurities (P). This is due to the electron transfer from substrate to the surface via Si-Cl bond. As a result, Si-Cl bond becomes more ionic and mobile, therefore the Cl-containing etchant forms $SiCl_x$ with surface more easily. Consequently, for the removal of Si atom from poly silicon surface, the chemical etching is more favorable than physical etching with increasing P concentrations.

• Proceedings of the Materials Research Society of Korea Conference
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• 2011.05a
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• pp.38.2-38.2
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• 2011

구리는 현재 반도체 배선으로 가장 많이 사용되는 재료이다. 배선기술이 발전함에 따라 배선두께가 얇아지게 되었고 배선간의 간격 또한 좁아지게 되었다. 간격의 감소는 RC delay 문제점을 야기하였고 이를 해결하기 위해 배선 사이에 Low-k물질을 채우는 노력이 지속되었다. 이상적으로 가장 낮은 유전율을 나타내는 물질은 공기 즉, 아무것도 채우지 않는 것이다. 하지만 이렇게 되면 기계적인 문제가 발생하는데 이를 해결하기 위해서 구리의 강도를 향상시켜야 한다. 강도를 높이려면 Hall-Petch 관계에 의해 결정립의 크기를 작게 만들어야 한다. 그렇지만 이는 곧 전기전도도의 감소를 나타내기 때문에 소자의 구동에 문제가 되어왔다. 이 문제를 해결하기 위해 펄스전해증착을 통한 나노사이즈의 쌍정구조를 가지는 구리의 개발이 진행되었다. 나노쌍정구리는 결정립이 정합면으로 이루어져 있는 쌍정구조로 이루어져 있어 전기전도도의 감소를 최소화하고 강도를 비약적으로 향상시킬 수 있을뿐더러 연신율도 높일 수 있다는 장점을 가지고 있다. 이렇게 고강도 저저항을 나타내는 나노쌍정구리는 Via filling, Through Silicon Via(TSV)에서의 칩간 연결 배선, 2차전지의 전극 등에 적용 가능성이 매우 높다. 이들은 주로 첨가제와 함께 전해증착을 통해 제작된다. 하지만 이러한 첨가제를 넣고 나노쌍정구리를 합성하기 위해 펄스전해증착을 시행할 경우, 나노 쌍정구리의 형성이 억제되고, Off-time이 존재하지 않는 일반 전해증착에서와는 다른 현상이 나타나게 된다. 이러한 이유로 본 연구에서는 현재 가장 많이 사용되고 있는 첨가제인 Poly (ethylene glycol) (PEG, 억제제)와 bis (3-sulfopropyl) disulfide (SPS, 가속제)을 사용하여 그 이유를 알아보고 첨가제를 사용하면서 나노쌍정구리의 밀도를 높일 수 있는 방안에 대해서 실험을 진행하였다.

• Korean Journal of Metals and Materials
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• v.48 no.7
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• pp.667-673
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• 2010

Copper filling into TSV (through-silicon-via) and reduction of the filling time for the three dimensional chip stacking were investigated in this study. A Si wafer with straight vias - $30\;{\mu}m$ in diameter and $60\;{\mu}m$ in depth with $200\;{\mu}m$ pitch - where the vias were drilled by DRIE (Deep Reactive Ion Etching) process, was prepared as a substrate. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. In order to reduce the time required complete the Cu filling into the TSV, the PPR (periodic pulse reverse) wave current was applied to the cathode of a Si chip during electroplating, and the PR (pulse-reverse) wave current was also applied for a comparison. The experimental results showed 100% filling rate into the TSV in one hour was achieved by the PPR electroplating process. At the interface between the Cu filling and Ti/ Au functional layers, no defect, such as a void, was found. Meanwhile, the electroplating by the PR current showed maximum 43% filling ratio into the TSV in an hour. The applied PPR wave form was confirmed to be effective to fill the TSV in a short time.

• Korean Journal of Metals and Materials
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• v.50 no.2
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• pp.152-158
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• 2012

The effect of current waveform on Cu filling into TSV (through-silicon via) and the bottom-up ratio of Cu were investigated for three dimensional (3D) Si chip stacking. The TSV was prepared on an Si wafer by DRIE (deep reactive ion etching); and its diameter and depth were 30 and $60{\mu}m$, respectively. $SiO_2$, Ti and Au layers were coated as functional layers on the via wall. The current waveform was varied like a pulse, PPR (periodic pulse reverse) and 3-step PPR. As experimental results, the bottom-up ratio by the pulsed current decreased with increasing current density, and showed a value of 0.38 on average. The bottom-up ratio by the PPR current showed a value of 1.4 at a current density of $-5.85mA/cm^2$, and a value of 0.91 on average. The bottom-up ratio by the 3-step PPR current increased from 1.73 to 5.88 with time. The Cu filling by the 3-step PPR demonstrated a typical bottom-up filling, and gave a sound filling in a short time.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.4
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• pp.9-17
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• 2017

In these days, MEMS (micro-electro-mechanical system) devices become the crucial sensor components in mobile devices, automobiles and several electronic consumer products. For MEMS devices, the packaging determines the performance, reliability, long-term stability and the total cost of the MEMS devices. Therefore, the packaging technology becomes a key issue for successful commercialization of MEMS devices. As the IoT and wearable devices are emerged as a future technology, the importance of the MEMS sensor keeps increasing. However, MEMS devices should meet several requirements such as ultra-miniaturization, low-power, low-cost as well as high performances and reliability. To meet those requirements, several innovative technologies are under development such as integration of MEMS and IC chip, TSV(through-silicon-via) technology and CMOS compatible MEMS fabrication. It is clear that MEMS packaging will be key technology in future MEMS. In this paper, we reviewed the recent development trends of the MEMS packaging. In particular, we discussed and reviewed the recent technology trends of the MEMS bonding technology, such as low temperature bonding, eutectic bonding and thermo-compression bonding.

• Journal of the Korean Ceramic Society
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• v.55 no.6
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• pp.562-569
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• 2018

We propose an economic and facile method for the preparation of silica nanoparticles through a two-step process utilizing chlorosilane residues. Mixed chlorosilane residue was alcoholized with absolute ethanol as a first step to form tetraethoxysilane (TEOS). The TEOS was then utilized as a silicon source to synthesize silica nanoparticles in a sol-gel method. The alcoholysis process was designed and optimized utilizing the Taguchi experimental design method and the yield of TEOS was as high as 82.2% under optimal synthetic conditions. Similarly, the Taguchi method was also utilized to study the effects of synthesis factors on the particle size of silica nanoparticles. The results of statistical analysis indicate that the concentration of ammonia has a greater influence on particle size compared to the mass fractions of TEOS and polyethylene glycol (4.6% and 9.7%). The purity of the silica particles synthesized in our experiments is high, but the specific surface area and pore volume are small.

• Journal of information and communication convergence engineering
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• v.12 no.3
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• pp.186-192
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• 2014

Monolithic three-dimensional integrated chips (3D ICs) are an emerging technology that offers an integration density that is some orders of magnitude higher than the conventional through-silicon-via (TSV)-based 3D ICs. This is due to a sequential integration process that enables extremely small monolithic inter-tier vias (MIVs). For a monolithic 3D memory, we first explore the static random-access memory (SRAM) design. Next, for digital logic, we explore several design styles. The first is transistor-level, which is a design style unique to monolithic 3D ICs that are enabled by the ultra-high-density of MIVs. We also explore gate-level and block-level design styles, which are available for TSV-based 3D ICs. For each of these design styles, we present techniques to obtain the graphic database system (GDS) layouts, and perform a signoff-quality performance and power analysis. We also discuss various challenges facing monolithic 3D ICs, such as achieving 50% footprint reduction over two-dimensional (2D) ICs, routing congestion, power delivery network design, and thermal issues. Finally, we present design techniques to overcome these challenges.

• Journal of the Korean Society for Precision Engineering
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• v.31 no.10
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• pp.865-871
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• 2014

Paradigm shift to 3-D chip stacking in electronic packaging has induced a lot of integration challenges due to the reduction in wafer thickness and pitch size. This study presents a hybrid bonding technology by self-alignment effect in order to improve the flip chip bonding accuracy with ultra-thin wafer. Optimization of Cu pillar bump formation and evaluation of various factors on self-alignment effect was performed. As a result, highly-improved bonding accuracy of thin wafer with a $50{\mu}m$ of thickness was achieved without solder bridging or bump misalignment by applying reflow process after thermo-compression bonding process. Reflow process caused the inherently-misaligned micro-bump to be aligned due to the interface tension between Si die and solder bump. Control of solder bump volume with respect to the chip dimension was the critical factor for self-alignment effect. This study indicated that bump design for 3D packaging could be tuned for the improvement of micro-bonding quality.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2017.05a
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• pp.70-70
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• 2017

TSV(through silicon via)는 긴 종횡비를 갖는 패턴에 Cu, Ta, Ti을 높은 conformality를 갖도록 증착하는 공정이다. Magnetron cathode의 자석 배열 설계는 target 물질 종류에 따라서 multitrack, water drop type등이 있으며 target과 substrate 사이의 공간에 플라즈마를 형성시켜서 기판에 이온 입사량을 늘린 후 기판 바이어스를 이용하여 이온 충돌, re-sputtering을 통한 재증착 과정을 통해 치밀한 금속 박막을 연속적으로 형성할 수 있도록 하는 것이 목적이다. 또한 sputter가 사용되고 있는 분야에 효율을 증대시키고, 증착되는 막의 품질향상을 위해 UBMS를 사용하고 있으며, 산업에 사용되어 지는 300 mm wafer용 시스템은 제작비가 약 10억 원 정도 소요되며 다양한 테스트를 진행하기 위해선 많은 비용이 소요된다. 따라서 비용과 소요시간을 줄여 다양한 테스트를 위해 소규모 플라즈마 시스템을 설계하게 되었다. 61 l/sec 터보 분자 펌프와 다이아프램 펌프를 기초로한 TMP station에 2.75 인치 CF flange가 장착된 6 way cross를 main 챔버로 활용하고, 작은 size의 unbalanced magnetron cathode를 제작, 장착한 다음 6 way cross 주변에 전자석을 적절히 배치하여 300 mm wafer system에서와 동일한 물리적 현상을 테스트 할 수 있도록 하였다. Fig1. (a) UBMS system의 사진을 나타내었고, (b)에는 6 way cross 내부에 발생된 플라즈마의 형상을 나타내었다. 전원 장치는 Advanced Energy사의 MDX-1.5K DC power supply를 사용하였고, 방전 전압 - 전류 관계의 가스 압력에 따른 plasma 현상과 magnetron 배율에 따른 plasma 현상 그리고 전자석에 의한 영향을 주로 관찰 하였다.