• Journal of Electrical Engineering and information Science
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• v.2 no.3
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• pp.132-138
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• 1997

Electrical characteristics of split-gate flash EEPROM with triple polysilicon is investigated in terms of effects of floating gate and offset gate. In order to search for t the effects of offset gate on programming characteristics, threshold voltage and drain current are studied with variation of control gate voltage. The programming process is believed to depend on vertical and horizontal electric field as well as offset gate length. The erase and program threshold voltage are found to be almost constant with variation of control gate voltage above 12V, while endurance test indicates degradation of program threshold voltage. With increase of offset gate length, program threshold voltage becomes smaller and the drain source voltage just after program under constant control gate voltage becomes higher.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2022.05a
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• pp.560-561
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• 2022

In this paper, current-voltage characteristics of various types of Nanosheet FET (NSFET) and FinFET are simulated with 3D device simulator. The threshold voltage and subthreshold swing extracted from the simulated current-voltage characteristics of NSFET and FinFET were compared. Both of threshold voltage and drain current of NSFET are higher than those of FinFET. The subthreshold voltage swing (SS) of NSFET is steeper than that of FinFET.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.7
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• pp.1311-1316
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• 2016

This paper analyzes the influence of tunneling current on threshold voltage shift by channel length of short channel asymmetric double gate(DG) MOSFET. Tunneling current significantly increases by decrease of channel length in the region of 10 nm below, and the secondary effects such as threshold voltage shift occurs. Threshold voltage shift due to tunneling current is not negligible even in case of asymmetric DGMOSFET to develop for reduction of short channel effects. Off current consists of thermionic and tunneling current, and the ratio of tunneling current is increasing with reduction of channel length. The WKB(Wentzel-Kramers-Brillouin) approximation is used to obtain tunneling current, and potential distribution in channel is hermeneutically derived. As a result, threshold voltage shift due to tunneling current is greatly occurred for decreasing of channel length in short channel asymmetric DGMOSFET. Threshold voltage is changing according to bottom gate voltages, but threshold voltage shifts is nearly constant.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.594-600
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• 2014

A threshold voltage compensation pixel circuit was developed for active-matrix organic light emitting diodes (AMOLEDs) using amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO-TFTs). Oxide TFTs are n-channel TFTs; therefore, we developed a circuit for the n-channel TFT characteristics. The proposed pixel circuit was verified and proved by circuit analysis and circuit simulations. The proposed circuit was able to compensate for the threshold voltage variations of the drive TFT in AMOLEDs. The error rate of the OLED current for a threshold voltage change of 3 V was as low as 1.5%.

• Journal of Electrical Engineering and Technology
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• v.9 no.6
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• pp.2079-2088
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• 2014

In this paper, we propose new physically based threshold voltage models for short channel Surrounding Gate Silicon Nanowire Transistor with two different geometries. The model explores the impact of various device parameters like silicon film thickness, film height, film width, gate oxide thickness, and drain bias on the threshold voltage behavior of a cylindrical surrounding gate and rectangular surrounding gate nanowire MOSFET. Threshold voltage roll-off and DIBL characteristics of these devices are also studied. Proposed models are clearly validated by comparing the simulations with the TCAD simulation for a wide range of device geometries.

• Electrical & Electronic Materials
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• v.9 no.8
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• pp.813-818
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• 1996

Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$ device shows the memory switching characteristics under d.c. bias. In bulk material, a-As$_{10}$Ge$_{15}$ Te$_{75}$ switching threshold voltage (V$_{th}$) is very high (above 100 volts), but in the case of thin film, V$_{th}$ decreases to a few or ten a few volts. The characteristics of V$_{th}$ depends on the physical dimensions such as the thickness of thin film and the separation between d.c. electrodes, and the annealing conditions. The switching threshold voltage decreases exponentially with increasing annealing temperature and annealing time, but increases linearly with the thickness of thin film and exponentially with increasing the separation between d.c. electrodes. The desirable low switching threshold voltage, therefore, can be obtained by the stabilization through annealing and changing physical dimensions.imensions.sions.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.29 no.7
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• pp.387-393
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• 2016

Threshold voltage shift has been observed from many thin-film transistors (TFTs) and the time evolution of the shift can be modeled as the stretched-exponential and -hyperbola function. These analytic models are derived from the kinetic equation for defect-creation or charge-trapping and the equation consists of only reversible reactions. In reality TFT's a shift is permanent due to an irreversible reaction and, as a result, it is reasonable to consider that both reversible and irreversible reactions exist in a TFT. In this paper the case when both reactions exist in parallel and make a combined threshold voltage shift is modeled and simulated. The results show that a combined threshold voltage shift observed from a TFT may agrees with the analytic models and, thus, the analytic models don't guarantee whether the cause of the shift is defection-creation or charge-trapping.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.111-120
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• 2011

A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.

• Journal of the Korean institute of surface engineering
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• v.50 no.5
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• pp.405-410
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• 2017

In order to study current-voltage-luminance and impedance characteristics according to elapsed time, a blue fluorescent OLED was fabricated. The current density and luminance gradually decreased in accordance with elapsed time and did not emit light after 480 hours, and the threshold voltage increased as time elapsed. The Cole-Cole plot was a semicircular shape of a very large size at 2 V of the applied voltage below the threshold voltage, and the maximum value of the real number impedance did not change greatly from 9314.5 to $9902.2{\Omega}$ as time elapsed. Applied voltages 4, 6, and 8 V above the threshold voltage showed a large change in the real number impedance value at the semicircle end to 9,678.2, 9,826, $9,535.4{\Omega}$ according to the elapsed time from 2,222.5, 183.7, $48.2{\Omega}$ immediately after fabricating the device. By increasing the applied voltage beyond the threshold voltage just after device fabrication, the energy difference between the device and the organic layer was overcome and the current flowed, the maximum value of the real number impedance sharply decreased. As time passed, current did not flow through the element even at high applied voltage due to degradation of the element, and even when the applied voltage was higher than the threshold voltage, it showed an impedance value such as applied voltage equal to or less than the threshold voltage. As a result, it can be learned that the change in the impedance with elapsed time reflects the characteristics due to the degradation of the OLED and can predict the characteristics and lifetime of the OLED.

• Journal of information and communication convergence engineering
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• v.13 no.4
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• pp.257-263
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• 2015

In this study, organic field-effect transistors (OFETs) using a copper phthalocyanine (CuPc) material as an active layer and SiO₂ as a gate insulator were fabricated with varying active layer thicknesses and channel lengths. Further, using a thermal evaporation method in a high-vacuum system, we fabricated a CuPc FET device of the top-contact type and used Au materials for the source and drain electrodes. In order to discuss the channel formation and FET characteristics, we observed the typical current-voltage characteristics and calculated the threshold voltage of the CuPc FET device. We also found that the capacitance reached approximately 97 pF at a negative applied voltage and increased upon the accumulation of carriers at the interface of the metal and the CuPc material. We observed the typical behavior of a FET when used as an n-channel FET. Moreover, we calculated the threshold voltage to be about 15-20 V at V_DS = -80 V.