• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.1243-1246
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• 2009

A novel a-Si TFT integrated gate driver circuit which suppresses the threshold voltage shift due to prolonged positive gate bias to pull-down TFTs, is reported. Negative gate-to-drain bias is applied alternately to the pull-down TFTs to recover the threshold voltage shift. Consequently, the stability of the circuit has been improved considerably.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.858-860
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• 2009

We have applied self-assembled monolayer to make high performance and stable OTFT on the organic gate dielectric. The ${\beta}$-phenethyltrichlorosilane (SAM) was coated on the organic gate dielectric and then active layer was printed. Significant improvements in on-currents and threshold voltage shift were achieved for the SAM treated devices compared to device without SAM.

• 전자공학회논문지A
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• 제31A권8호
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• pp.34-45
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• 1994

We studied threshold voltages and I-V characteristics. considering short channel effect of the fully depleted thin film n-channel SOI MOSFET. We presented a charge sharing model when the back surface of short channel shows accumulation depletion and inversion state respectively. A degree of charge sharing can be compared according to each of back-surface conditions. Mobility is not assumed as constant and besides bulk mobility both the mobility defined by acoustic phonon scattering and the mobility by surface roughness scattering are taken into consideration. I-V characteristics is then implemented by the mobility including vertical and parallel electric field. kThe validity of the model is proved with the 2-dimensional device simulation (MEDICI) and experimental results. The threshold voltage and charge sharing region controlled by source or drain reduced with increasing back gate voltage. The mobility is dependent upon scattering effect and electric field. so it has a strong influence on I-V characteristics.

• Journal of Electrical Engineering and Technology
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• 제9권2호
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• pp.609-614
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• 2014

We fabricated amorphous zinc tin oxide (ZTO) transparent thin-film transistors (TTFTs). The effects of Al electrode on the mobility and threshold voltage of the ZTO TTFTs were investigated. It was found that the aluminum (Al)-ZTO contact decreased the mobility and increased the threshold voltage. Traps, originating from $AlO_x$, were assumed to be the cause of degradation. An indium tin oxide film was inserted between Al and ZTO as a buffer layer, forming an ohmic contact, which was revealed to improve the performance of ZTO TTFTs.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.199-201
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• 1994

The switching characteristics of $As_{10}Ge_{15}Te_{75}$ thin film were investigated under dc bias. It was found that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively. The threshold voltage is increased as the thickness and the electrode distance is increased, while the threshold voltage is decreased in proportion to the increased annealing time and temperature.

• 한국정보통신학회:학술대회논문집
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• 한국해양정보통신학회 2005년도 춘계종합학술대회
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• pp.981-984
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• 2005

본 논문에서는 전하트랩형 SONOS 메모리에서 프로그래밍 동작 후 변화되는 문턱전압을 시뮬레이션에 의하여 구현하고자 한다. SONOS 소자는 질화막내의 트랩 뿐 만아니라, 질화막-블로킹산화막 계면에 존재하는 트랩에 전하를 저장하는 전하트랩형 비휘발성기억소자로서, 기억상태에 따른 문턱전압을 시뮬레이션으로 구현하기위해서는 질화막내의 트랩을 정의할 수 있어야 된다. 그러나 기존의 시뮬레이터에서는 질화막내의 트랩모델이 개발되어 있지 않은 것이 현실이다. 따라서 본 연구에서는 SONOS 구조의 터널링산화막-질화막 계면과 질화막-블로킹산화막 계면에 두개의 전극을 정의하여 프로그램 전압과 시간에 따라서 전극에 유기되는 전하량으로부터 전하트랩형 기억소자의 문턱전압변화를 시뮬레이션 할 수 있는 새로운 방법을 제안한다.

• 대한임상전기생리학회지
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• 제4권1호
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• pp.1-12
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• 2006

This study conducted RIII reflex measurement to examine degree of pain depending on polarity of high voltage pulsed current of primary and secondary hyperalgesia site in hyperalgesia rat by local thermal injury. Hind paw which was injury site was taken as primary hyperalgeisa site, sole which was injury adjacent site was taken as secondary hyperalgesia site, and mechanical pain threshold, thermal pain threshold and root mean square of RIII reflex were measured. This study was conducted with control group I of hyperalgesia rat at hind paw by thermal injury and experimental groups divided into cathodal high voltage treatment group II, anodal high voltage treatment group III and alternate high voltage treatment group IV, applied active electrode of high voltage pulsed current to hind paw directly, placed reference electrode on the sole of injury adjacent site and applied pulse frequency. It measured RIII reflex and obtained the following results: Root mean square of RIII reflex at primary hyperalgeisa site was significantly reduced in group II after 2 days of hyperalgesia. Group II showed significant decrease after 5 and 6 days of hyperalgesia. Root mean square of RIII reflex at secondary hyperalgesia site showed significant reduction in group II after 6 days of hyperalgesia. Consequently it was found that application of high voltage pulsed current of hyperalgesia site reduced RIII reflex at primary hyperalgeisa site and secondary hyperalgesia site by electrical stimuli. Effects by polarity of high voltage pulsed current showed the greatest reduction of pain threshold when cathodal active electrode was used.

• JSTS:Journal of Semiconductor Technology and Science
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• 제7권2호
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• pp.67-75
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• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.473-481
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• 2012

For a mesa-isolated small geometry SOI MOSFET, the potentials in the silicon film, front, back, and side-wall oxide layers can be derived three-dimensionally. Using Taylor's series expansions of the trigonometric functions, the derived potentials are written in terms of the natural length that can be determined by using the derived formula. From the derived 3-D potentials, the minimum values of the front and the back surface potentials are derived and used to obtain the closed-form expressions for the front and back gate threshold voltages as functions of various device parameters and applied bias voltages. Obtained results can be found to explain the drain-induced threshold voltage roll-off and the narrow width effect of a fully depleted small geometry SOI MOSFET in a unified manner.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1105-1108
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• 2003

In this paper, we have fabricated the hydrogenated n-channel polysilicon thin film transistor (TFT) with LDD structure and have analyzed the hot carrier degradation characteristics by electrical stress. We have compared the threshold voltage (Vth), sub-threshold slope (S), and trans-conductance (Gm) for devices with LDD (Lightly Doped Drain) structure and non-LDD at same active sizes. We have analyzed the hot carrier effects by the hydrogenation in devices. As a analyzed results, the threshold voltage, sub-threshold slope for n-channel poly-si TFT were increased, trans-conductance was decreased. The effects of hydrogenation in n-channel poly-si TFT with LDD structure were shown the lower variations of characteristics than devices of the non-LDD structure with nomal process.