• ETRI Journal
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• 제31권6호
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• pp.653-659
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• 2009

We have investigated the channel protection layer (PL) effect on the performance of an oxide thin film transistor (TFT) with a staggered top gate ZnO TFT and Al-doped zinc tin oxide (AZTO) TFT. Deposition of an ultra-thin PL on oxide semiconductor films enables TFTs to behave well by protecting the channel from a photo-resist (PR) stripper which removes the depleted surface of the active layer and increases the carrier amount in the channel. In addition, adopting a PL prevents channel contamination from the organic PR and results in high mobility and small subthreshold swings. The PL process plays a critical role in the performance of oxide TFTs. When a plasma process is introduced on the surface of an active layer during the PL process, and as the plasma power is increased, the TFT characteristics degrade, resulting in lower mobility and higher threshold voltage. Therefore, it is very important to form an interface using a minimized plasma process.

• 한국세라믹학회지
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• 제52권3호
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• pp.209-214
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• 2015

Silicon nitride films were deposited at $100^{\circ}C$ by using the catalytic chemical vapor deposition technique. The source gas mixing ratio, $R_N=[NH_3]/[SiH_4]$, was varied from 10 to 30, and the hydrogen dilution ratio, $R_H=[H_2]/[SiH_4]$, was varied from 20 to 100. The breakdown field strength reached a maximum value at $R_N=20$ and $R_H=20$, whereas the resistivity decreased in the same sample. The relative permittivity had a positive correlation with the breakdown field strength. The capacitance-voltage threshold curve showed an asymmetric hysteresis loop, which became more squared as $R_H$ increased. The width of the hysteresis window showed a negative correlation with the slope of the transition region, implying that the combined effect of $R_N$ and $R_H$ overides the interface defects while creating charge storage sites in the bulk region.

• 한국결정성장학회지
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• 제9권5호
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• pp.459-462
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• 1999

Recent advances in NLO Borate Crystals for UV Generation are reviewed with the particular emphasis on the technique to improve the life time of UV optics. The laser-damage resistance of CLBO and fused silica surfaces was successfully improved after removing polishing compound by ion beam etching. The polishing compound embedded in the CLBO and fused silica surfaces were to a depth of less than 100nm. We were able to remove polishing compound without degrading the surface condition when the applied ion beam voltage was less than 200 V. The laser-induced surface damage threshold of CLBO was improved up to 15J/$\textrm{cm}^2$(wavelength: 355 nm, pulse width: 0.85 ns)as compared with that of the as-polished surface (11 J/$\textrm{cm}^2$). The laser-induced surface damage of fused silica also increased from 7.5J/$\textrm{cm}^2$ to 15J/$\textrm{cm}^2$. For the irradiation of a 266 nm high-intensity and high-repetition laser light, the surface lifetime of CLBO and fused silica could be more doubled compared with that of the as-polished surface.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2008년도 하계학술대회 논문집 Vol.9
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• pp.182-183
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• 2008

We fabricated a pentacene thin film transistor with Poly-vinylalcohol (PVA) as a dielectric. And we used Poly(9-vinylcarbazole) (PVK) as a buffer layer to improve the electrical characteristics. PVK is a material used often host material for OLED device, as it has good film forming properties, large HOMO-LUMO(highest occupied molecular orbital-lowest unoccupied molecular orbital) bandgap. The performance of a OTFT device with PVA gate dielectric was improved by using the PVK. Field effect mobility, threshold voltage, and on-off current ratio of device with PVK layer were about 0.6 $cm^2$/Vs, -17V, and $5\times10^5$, respectively.

• 한국전기전자재료학회논문지
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• 제29권12호
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• pp.750-758
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• 2016

For the channel doping of shallow junction and retrograde well formation in CMOS, indium can be implanted in silicon. The retrograde doping profiles can serve the needs of channel engineering in deep MOS devices for punch-through suppression and threshold voltage control. Indium is heavier element than B, $BF_2$ and Ga ions. It also has low coefficient of diffusion at high temperatures. Indium ions can be cause the erode of wafer surface during the implantation process due to sputtering. For the ultra shallow junction, indium ions can be implanted for p-doping in silicon. UT-MARLOWE and SRIM as Monte carlo ion-implant models have been developed for indium implantation into single crystal and amorphous silicon, respectively. An analytical tool was used to carry out for the annealing process from the extracted simulation data. For the 1D (one-dimensional) and 2D (two-dimensional) diffused profiles, the analytical model is also developed a simulation program with $C^{{+}{+}}$ code. It is very useful to simulate the indium profiles in implanted and annealed silicon autonomously. The fundamental ion-solid interactions and sputtering effects of ion implantation are discussed and explained using SRIM and T-dyn programs. The exact control of indium doping profiles can be suggested as a future technology for the extreme shallow junction in the fabrication process of integrated circuits.

• 전기학회논문지
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• 제59권2호
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• pp.369-373
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• 2010

Modem electronic circuits are of importance for the function of communication, traffic systems and security systems. An intentional threat to these systems could be of big casualties and economic disasters. This paper has shown damage effect of microcontroller device with coupling caused by UWB-HPEM(Ultra Wideband-High Power Electromagnetics). The UWB measurements were done at an Anechoic Chamber using a RADAN UWB voltage source, which can generate a transient impulse of about 180 kV. The susceptibility level for microcontroller has been assessed by effect of various operation line lengths. The results of susceptibility analysis has showed that the effect of the reset line length on the MT(Ma1function Threshold) is larger than the effect of the different line length(Data, Power, Clock). With the knowledge of these parameters electronic system can be designed exactly suitable concerning the system requirements. Based on the results, susceptibility of microcontroller can be applied to protection plan to elucidate the effects of microwaves on electronic equipment.

• 전기학회논문지
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• 제58권2호
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• pp.342-348
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• 2009

This paper introduces a novel denoising algorithm for the partial-discharge(PD) signals from power apparatuses. The developed algorithm includes three kinds of specific denoising sub-algorithms. The first sub-algorithm uses the fuzzy logic which classifies the noise types in the magnitude versus phase PD pattern. This sub-algorithm is especially effective in the rejection of the noise with high and constant magnitude. The second one is the method simply removing the pulses in the phase sections below the threshold count in the count versus phase pattern. This method is effective in removing the occasional high level noise pulses. The last denoising sub-algorithm uses the grouping characteristics of PD pulses in the 3D plot of the magnitude versus phase versus cycle. This special technique can remove the periodical noise pulses with varying magnitudes, which are very difficult to be removed by other denoising methods. Each of the sub-algorithm has different characteristic and shows different quality of the noise rejection. On that account, a parameter which numerically expresses the noise possessing degree of signal, is defined and evaluated. Using the parameter and above three sub-algorithms, an adaptive complex noise rejection algorithm for the on-line PD diagnosis system is developed. Proposed algorithm shows good performances in the various real PD signals measured from the power apparatuses in the Korean plants.

• 전력전자학회논문지
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• 제20권6호
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.389-392
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• 2009

Metal oxides have been proposed as an alternative channel material to hydrogenated amorphous silicon in thin film transistors (TFTs) because their higher mobility and stability make them suitable for transistor active layers. Thin films of indium zinc oxide (IZO) were deposited using a High Target Utilization Sputtering (HiTUS) system on various dielectrics, some of which were also deposited with the HiTUS. Investigations into bottom-gated IZO TFTs have found mobilities of 8 $cm^2V\;^1s^{-1}$ and switching ratios of $10^6$. There is a variation in the threshold voltage dependent on both oxygen concentration, and dielectric choice. Silica, alumina and silicon nitride produced stable TFTs, whilst hafnia was found to break down as a result of the IZO.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2009년도 9th International Meeting on Information Display
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• pp.953-956
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• 2009

We have investigated the effect of light on amorphous silicon thin film transistors based photo-sensor applications. We have analyzed the instability caused by electrical gate bias stresses under the light illumination and the effect of photo-induced quasi-annealing on the instability. Threshold voltage ($V_{TH}$) under the negative gate bias stress with light illumination was more decreased than that under the negative gate bias stress without light illumination even though $V_{TH}$ caused by the light-induced stress without negative gate bias was shifted positively. These results are because the increase of carrier density in a channel region caused by the light illumination has the enhanced effect on the instability caused by negative gate bias stress. The prolonged light illumination led to the recovery of shifted VTH caused by negative gate bias stress under the light illumination due to the recombination of trapped hole charges.