• The Transactions of the Korean Institute of Electrical Engineers
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• v.43 no.6
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• pp.869-876
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• 1994

This paper presents an efficient method to calculate voltage collapse point and to avoid voltage instability. To evaluate voltage stability in power systems, it is necessary to get critical loading points. For this purpose, this paper uses linear programming to calculate efficiently voltage collapse point. Also, if index value becomes larger than given threshold value, voltage stability is improved by compensation of reactive power at selected bus. This algorithm is verified by simulation on the IEEE 14-bus sample system.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.88-93
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• 2020

Based on the capture-emission energy (CEE) maps of CMOS devices, a physics-informed machine learning model for the bias temperature instability (BTI)-induced threshold voltage shifts and low frequency noise is presented. In order to incorporate physics theories into the machine learning model, the integration of artificial neural network (IANN) is employed for the computation of the threshold voltage shifts and low frequency noise. The model combines the computational efficiency of IANN with the optimal estimation of Gaussian mixture model (GMM) with soft clustering. It enables full lifetime prediction of BTI under various stress and recovery conditions and provides accurate prediction of the dynamic behavior of the original measured data.

• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.2
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• pp.79-99
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• 2010

Pulsed current-voltage (I-V) methods are introduced to evaluate the impact of fast transient charge trapping on the performance of high-k dielectric transistors. Several pulsed I-V measurement configurations and measurement requirements are critically reviewed. Properly configured pulsed I-V measurements are shown to be capable of extracting such device characteristics as trap-free mobility, trap-induced threshold voltage shift (${\Delta}V_t$), as well as effective fast transient trap density. The results demonstrate that the pulsed I-V measurements are an essential technique for evaluating high-$\kappa$ gate dielectric devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.23 no.7
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• pp.545-549
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• 2010

Low-frequency noise (1/f noise) has been measured in order to analyze the Vth instability of ZnO TFTs having two different active layer thicknesses of 40 nm and 80 nm. Under electrical stress, it was found that the TFTs with the active layer thickness of 80 nm shows smaller threshold voltage shift (${\Delta}V_{th}$) than those with thickness of 40 nm. However the ${\Delta}V_{th}$ is completely relaxed after the removal of DC stress. In order to investigate the cause of this threshold voltage instability, we accomplished the 1/f noise measurement and found that ZnO TFTs exposed the mobility fluctuation properties, in which the noise level increases as the gate bias rises and the normalized drain current noise level($S_{ID}/{I_D}^2$) of the active layer of thickness 80 nm is smaller than that of active layer thickness of thickness 40 nm. This result means that the 80 nm thickness TFTs have a smaller density of traps. This result correlated with the physical characteristics analysis performmed using XRD, which indicated that the grain size increases when the active layer thickness is made thicker. Consequently, the number of preexisting traps in the device increases with decreasing thickness of the active layer and are related closely to the $V_{th}$ instability under electrical stress.

• Transactions on Electrical and Electronic Materials
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• v.18 no.1
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• Transactions on Electrical and Electronic Materials
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• v.15 no.6
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• pp.315-319
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• 2014

In this paper, we investigate visible light stress instability in radio frequency (RF) sputtered a-IGZO thin film transistors (TFTs). The oxygen flow rate differs during deposition to control the concentration of oxygen vacancies, which is confirmed via RT PL. A negative shift is observed in the threshold voltage ($V_{TH}$) under illumination with/without the gate bias, and the amount of shift in $V_{TH}$ is proportional to the concentration of oxygen vacancies. This can be explained to be consistent with the ionization oxygen vacancy model where the instability in $V_{TH}$ under illumination is caused by the increase in the channel conductivity by electrons that are photo-generated from oxygen vacancies, and it is maintained after the illumination is removed due to the negative-U center properties.

• Journal of Sensor Science and Technology
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• v.28 no.5
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• pp.329-333
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• 2019

Solution-processed oxide thin-film transistors (TFTs) have garnered great attention, owing to their many advantages, such as low-cost, large area available for fabrication, mechanical flexibility, and optical transparency. Negative bias stress (NBS)-induced instability of sol-gel IGZO TFTs is one of the biggest concerns arising in practical applications. Thus, understanding the bias stress effect on the electrical properties of sol-gel IGZO TFTs and proposing an effective recovery method for negative bias stressed TFTs is required. In this study, we investigated the variation of transfer characteristics and the corresponding electrical parameters of sol-gel IGZO TFTs caused by NBS and positive bias recovery (PBR). Furthermore, we proposed an effective PBR method for the recovery of negative bias stressed sol-gel IGZO TFTs. The threshold voltage and field-effect mobility were affected by NBS and PBR, while current on/off ratio and sub-threshold swing were not significantly affected. The transfer characteristic of negative bias stressed IGZO TFTs increased in the positive direction after applying PBR with a negative drain voltage, compared to PBR with a positive drain voltage or a drain voltage of 0 V. These results are expected to contribute to the reduction of recovery time of negative bias stressed sol-gel IGZO TFTs.

• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• Journal of Electrical Engineering and Technology
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• v.10 no.3
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• pp.877-887
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• 2015

Rapid development of cities with constant increasing load and deregulation in electricity market had forced the transmission lines to operate near their threshold capacity and can easily lead to voltage instability and caused system breakdown. To prevent such catastrophe from happening, accurate readings of voltage stability condition is required so that preventive equipment and operators can execute security procedures to restore system condition to normal. This paper introduced Enhanced Hybrid Particle Swarm Optimization algorithm to estimate the voltage stability condition which utilized Fast Voltage Stability Index (FVSI) to indicate how far or close is the power system network to the collapse point when the reactive load in the system increases because reactive load gives the highest impact to the stability of the system as it varies. Particle Swarm Optimization (PSO) had been combined with the ANN to form the Enhanced Hybrid PSO-ANN (EHPSO-ANN) algorithm that worked accurately as a prediction algorithm. The proposed algorithm reduced serious local minima convergence of ANN but also maintaining the fast convergence speed of PSO. The results show that the hybrid algorithm has greater prediction accuracy than those comparing algorithms. High generalization ability was found in the proposed algorithm.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.32 no.5
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• pp.371-375
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• 2019

Developing a thin-film transistor with characteristics such as a large area, high mobility, and high reliability are key elements required for the next generation on displays. In this paper, we have investigated the research trends related to improving the reliability of oxide-semiconductor-based thin-film transistors, which are the primary focus of study in the field of optical displays. It has been reported that thermal treatment in a high-pressure oxygen atmosphere reduces the threshold voltage shift from -7.1 V to -1.9 V under NBIS. Additionally, a device with a $SiO_2/Si_3N_4$ dual-structure has a lower threshold voltage (-0.82 V) under NBIS than a single-gate-insulator-based device (-11.6 V). The dual channel structure with different oxygen partial pressures was also confirmed to have a stable threshold voltage under NBIS. These can be considered for further study to improve the NBIS problem.