• 제목/요약/키워드: Three-level (NPC) inverter

검색결과 73건 처리시간 0.018초

영 전위 중성점을 가진 새로운 3상 Three-Level 스위치 전압원 인버터 (Three Phase Three-Level Switched Voltage Source PWM Inverter with Zero Neutral Point Potential)

  • 오원식;한상규;최성욱;문건우
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2004년도 전력전자학술대회 논문집(2)
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    • pp.630-634
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    • 2004
  • A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. The major advantage is that the peak value of the phase output voltage is twice as high as that of the conventional neutral-point-clamped (NPC) PWM inverter. Furthermore, three-level waveforms of the proposed inverter can be achieved without switch voltage unbalance problem. Since the average neutral point potential of the proposed inverter is zero, the common ground between input stage and output stage is possible. The proposed inverter is verified by experimental results based on a laboratory prototype.

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DSP-Based Simplified Space-Vector PWM for a Three-Level VSI with Experimental Validation

  • Ramirez, Jose Dario Betanzos;Rivas, Jaime Jose Rodriguez;Peralta-Sanchez, Edgar
    • Journal of Power Electronics
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    • 제12권2호
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    • pp.285-293
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    • 2012
  • Multilevel inverters have gained attention in high-power applications due to their numerous advantages in comparison with conventional two-level inverters. In this paper a simplified Space-Vector Modulation (SVM) algorithm for a three-level Neutral-Point Clamped (NPC) inverter is implemented on a Freescale$^{(R)}$ DSP56F8037. The algorithm is based on a simplification of the space-vector diagram for a three-level inverter so that it can be used with a two-level inverter. Once the simplification has been achieved, calculation of the dwell times and the switching sequences are carried out in the same way as for the two-level SVM method. Details of the hardware design are included. Experimental results are analyzed to validate the performance of the simplified algorithm.

삼상 3레벨 NPC 인버터와 T-type 인버터의 효율적 선택을 위한 비교 분석 (Comparison for efficient selection of Three-phase Three Level NPC and T-type Inverter)

  • 박주영;박종훈;최재호
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2015년도 추계학술대회 논문집
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    • pp.135-136
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    • 2015
  • 대용량 분산 발전원이 증가하면서 이러한 대용량 분산 발전을 효율적으로 운전하기 위한 많은 연구가 진행되고 있다. 본 논문에서는 멀티레벨 인버터 토폴로지 중 NPC와 T-type 인버터의 중성점 전압제어를 통해 두 개의 멀티레벨 인버터에서 발생하는 효율과 제어방식의 차이를 시뮬레이션하고 비교 분석하였다.

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A Simple Control Strategy for Balancing the DC-link Voltage of Neutral-Point-Clamped Inverter at Low Modulation Index

  • C.S. Ma;Kim, T.J.;D.W. Kang;D.S. Hyun
    • Journal of Power Electronics
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    • 제3권4호
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    • pp.205-214
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    • 2003
  • This paper proposes a simple control strategy based on the discontinuous PWM (DPWM) to balance the DC-link voltage of three-level neutral-point-clamped (NPC) inverter at low modulation index. It introduces new DPWM methods in multi-level inverter and one of them is used for balancing the DC-link voltage. The current flowing in the neutral point of the DC-link causes the fluctuation of the DC-link voltage of the NPC inverter. The proposed DPWM method changes the path and duration time of the neutral point current, which makes the overall fluctuation of the DC-link voltage zero during a sampling time of the reference voltage vector. Therefore, by using the proposed strategy, the voltage of the DC-link can be balanced fairly well and the voltage ripple of the DC-link is also reduced significantly. Moreover, comparing with conventional methods which have to perform the complicated calculation, the proposed strategy is very simple. The validity of the proposed DPWM method is verified by the experiment.

Capacitor Voltage Boosting and Balancing using a TLBC for Three-Level NPC Inverter Fed RDC-less PMSM Drives

  • Halder, Sukanta;Kotturu, Janardhana;Agarwal, Pramod;Srivastava, Satya Prakash
    • Journal of Power Electronics
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    • 제18권2호
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    • pp.432-444
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    • 2018
  • This paper presents a capacitor voltage balancing topology using a three-level boost converter (TLBC) for a neutral point clamped (NPC) three-level inverter fed surface permanent magnet synchronous motor drive (SPMSM). It enhanced the performance of the drive in terms of its voltage THD and torque pulsation. The main attracting feature of the proposed control is the boosting of the input voltage and at the same time the balancing of the capacitor voltages. This control also reduces the computational complexity. For the purpose of close loop vector control, a software based cost effective resolver to digital converter RDC-less estimation is implemented to calculate the speed and position. The proposed drive is simulated in the MATLAB/SIMULINK environment and an experimental investigation using dSPACE DS1104 validates the proposed drive system at different operating condition.

Analysis and Control of NPC-3L Inverter Fed Dual Three-Phase PMSM Drives Considering their Asymmetric Factors

  • Chen, Jian;Wang, Zheng;Wang, Yibo;Cheng, Ming
    • Journal of Power Electronics
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    • 제17권6호
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    • pp.1500-1511
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    • 2017
  • The purpose of this paper is to study a high-performance control scheme for neutral-point-clamping three-level (NPC-3L) inverter fed dual three-phase permanent magnet synchronous motor (PMSM) drives by considering some asymmetric factors such as the non-identical parameters in phase windings. To implement this, the system model is analyzed for dual three-phase PMSM drives with asymmetric factors based on the vector space decomposition (VSD) principle. Based on the equivalent circuits, PI controllers with feedforward compensation are used in the d-q subspace for regulating torque, where the cut-off frequency of the PI controllers are set at the twice the fundamental frequency for compensating both the additional DC component and the second order component caused by asymmetry. Meanwhile, proportional resonant (PR) controllers are proposed in the x-y subspace for suppressing the possible unbalanced currents in the phase windings. A dual three-phase space vector modulation (DT-SVM) is designed for the drive, and the balancing factor is designed based on the numerical fitting surface for balancing the DC link capacitor voltages. Experimental results are given to demonstrate the validity of the theoretical analysis and the proposed control scheme.

Carrier Phase-Shift PWM to Reduce Common-Mode Voltage for Three-Level T-Type NPC Inverters

  • Nguyen, Tuyen D.;Phan, Dzung Quoc;Dao, Dat Ngoc;Lee, Hong-Hee
    • Journal of Power Electronics
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    • 제14권6호
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    • pp.1197-1207
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    • 2014
  • Common-mode voltage (CMV) causes overvoltage stress to winding insulation and damages AC motors. CMV with high dv/dt causes leakage currents, which create noise problems for equipment installed near the converter. This study proposes a new pulse-width modulation (PWM) strategy for three-level T-type NPC inverters. This strategy substantially eliminates CMV. The principle for selecting suitable triangle carrier signals for the three-level T-type NPC is described. The proposed method can mitigate the peak value of CMV by 50% compared with the phase disposition pulse-width modulation method. Furthermore, the proposed method exhibits better harmonic spectrum and lower root mean square value for the CMV than those of the reduced-CMV method on the basis of the phase opposition disposition PWM scheme with modulation index higher than 0.5. The proposed modulation can easily be implemented using software without any additional hardware modifications. Both simulation and experimental results demonstrate that the proposed carrier phase-shift PWM method has good output waveform performance and reduces CMV.

A Three Phase Three-level PWM Switched Voltage Source Inverter with Zero Neutral Point Potential

  • Oh Won-Sik;Han Sang-Kyoo;Choi Seong-Wook;Moon Gun-Woo
    • Journal of Power Electronics
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    • 제5권3호
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    • pp.224-232
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    • 2005
  • A new three phase three-level Pulse Width Modulation (PWM) Switched Voltage Source (SVS) inverter with zero neutral point potential is proposed. It consists of three single-phase inverter modules. Each module is composed of a switched voltage source and inverter switches. The major advantage is that the peak value of the phase output voltage is twice as high as that of a conventional neutral-point-clamped (NPC) PWM inverter. Thus, the proposed inverter is suitable for applications with low voltage sources such as batteries, fuel cells, or solar cells. Furthermore, three-level waveforms of the proposed inverter can be achieved without the switch voltage imbalance problem. Since the average neutral point potential of the proposed inverter is zero, a common ground between the input stage and the output stage is possible. Therefore, it can be applied to a transformer-less Power Conditioning System (PCS). The proposed inverter is verified by a PSpice simulation and experimental results based on a laboratory prototype.

A New DPWM Method to Suppress the Low Frequency Oscillation of the Neutral-Point Voltage for NPC Three-Level Inverters

  • Lyu, Jianguo;Hu, Wenbin;Wu, Fuyun;Yao, Kai;Wu, Junji
    • Journal of Power Electronics
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    • 제15권5호
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    • pp.1207-1216
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    • 2015
  • In order to suppress the low frequency oscillation of the neutral-point voltage for three-level inverters, this paper proposes a new discontinuous pulse width modulation (DPWM) control method. The conventional sinusoidal pulse width modulation (SPWM) control has no effect on balancing the neutral-point voltage. Based on the basic control principle of DPWM, the relationship between the reference space voltage vector and the neutral-point current is analyzed. The proposed method suppresses the low frequency oscillation of the neutral-point voltage by keeping the switches of a certain phase no switching in one carrier cycle. So the operating time of the positive and negative small vectors is equal. Comparing with the conventional SPWM control method, the proposed DPWM control method suppresses the low frequency oscillation of the neutral-point voltage, decreases the output waveform harmonics, and increases both the output waveform quality and the system efficiency. An experiment has been realized by a neutral-point clamped (NPC) three-level inverter prototype based on STM32F407-CPLD. The experimental results verify the correctness of the theoretical analysis and the effectiveness of the proposed DPWM method.

4MW급 고압 인버터 시스템 개발 (Development of 4MW Class High Voltage Inverter System)

  • 박영민;한기준;최세경;정명길;이세현
    • 전력전자학회논문지
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    • 제6권5호
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    • pp.432-437
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    • 2001
  • 본 연구는 새로이 개발된 3.3KV 4MW급의 3레벨 NPC구조의 전압형 대용량 인버터에 대한 것으로 Web 기반의 인버터 정보 관리 시스템(Inverter Information Management System)과 가상 운전 시뮬레이터가 부가된 것이다. 사용된 전동기 제어 알고리즘은 속도 센서 없이 동작 가능한 DTC(Direct Torque Control)기법으로 빠른 응답특성을 갖고 있다. IIMS는 운전상태 모니터링 및 Data 관리기능을 가지고 있으며 가상 운전시뮬레이터는 주 전원을 공급하지 않은 상태에서 시스템의 특성 검증 및 Tuning이 가능하다. 현재 이 제품은 신뢰성 검증을 위해 현장 시험 중에 있다.

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