• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.193-193
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• 2011

To obtain ceramic films, the sol-gel coating technique has been broadly used with heat treatment, but crack formation tend to occur during heat treatment in thick sol-gel films. We prepared PZT thin films by sol-gel method with single-step spin coating process. The PZT solution have been synthesized using lead acetate ($Pb(CH_3COO)_2$), zirconium acetylacetonate ($Zr(OC_3H_7^n)_4$), and titanium diisopropoxide bis(acetylacetonate) 75wt% in isopropanol ($Ti(OC_3H_7^i)_2(OC_3H_7^n)_2$) as starting materials and n-propanol was selected as a solvent. The poly(vynilpyrrolidone) (PVP) was added with 0, 0.25, 0.5, 0.75, and 1 molar ratios to control viscosity of solution. We investigated influence of the viscosity on thickness, microstructure, and electrical properties of final PZT films. Thermo-gravimetric analysis and differential scanning calorimeter (TGA/DSC) was carried out from room temperature to $800^{\circ}C$ in order to measure pyrolysis temperature. Structural characteristics were analyzed by X-ray diffraction (XRD) and scanning electron microscopy (SEM). Ferroelectric and dielectric properties were measured by RT66A (Radiant) and impedance analyzer (Agilent), respectively. The thicknesses of PZT films depended on incorporation of an excess amount of PVP. Finally, we obtained PZT films of good quality without crack formation via single-step spin coating.

• Journal of the Korean Applied Science and Technology
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• v.24 no.1
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• pp.54-60
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• 2007

이 논문에서는 게이트 절연막 위에 vapor deposition polymerization(VDP)방법을 사용하여 성막한 유기 점착층을 진공 열증착하여 유기 박막 트랜지스터(OTFTs)소자를 제작할 수 있음을 증명하였다. 우리가 제작한 Staggered-inverted top-contact 구조를 사용한 유기 박막 트랜지스터는 전기적 output 특성이 포화 영역안에서는 포화곡선을, triode 영역에서는 비선형적인 subthreshold를 확실히 볼 수 있음을 발견했다. $0.2{\mu}m$ 두께를 가진 게이트 절연막위에 유기 점착층을 사용한 OTFTs의 장 효과 정공의 이동도와 문턱전압, 그리고 절멸비는 각각, 약 0.4cm2/Vs, -0.8V, 106 이 측정되었다. 게이트 절연막의 점착층으로써 폴리이미드의 성막을 위해, 스핀코팅 방법 대신 VDP 방법을 도입하였다. 폴리이미드 고분자막은 2,2bis(3,4-dicarboxyphenyl)hexafluoropropane dianhydride(6FDA)와 4,4'-oxydianiline(ODA)을 고진공에서 동시에 열 증착 시킨 후, 그리고 $150^{\circ}C$에서 1시간, 다시 $200^{\circ}C$에서 1시간 열처리하여 고분자화된 막을 형성하였다. 그리고 점착층이 OTFTs의 전기적 특성에 주는 영향을 설명하기 위해 비교 연구하였다.

• Journal of Adhesion and Interface
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• v.20 no.4
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• pp.155-161
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• 2019

Understanding charge transport anisotropy at the interface of conjugated nanostructures basically gives insight into structure-property relationship in organic field-effect transistors (OFET). Here, the anisotropy of the field-effect mobility at the interface between 6,13-bis(triisopropylsilylethynyl) pentacene (TIPS-pentacene) single crystal with cofacial molecular stacks in a-b basal plane and SiO gate dielectric was investigated. A solvent exchange method has been used in order for TIPS-pentacene single crystals to be grown on the surface of SiO₂ thin film, corresponding to the charge accumulation at the interface in OFET structure. In TIPS-pentacene OFET, the anisotropy ratio between the highest and lowest measured mobility is revealed to be 5.2. By analyzing the interaction of a conjugated unit in TIPS-pentacene with the nearest neighbor units, the mobility anisotropy can be rationalized by differences in HOMO-level coupling and hopping routes of charge carriers. The theoretical estimation of anisotropy based on HOMO-level coupling is also consistent with the experimental result.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.168-168
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• 2008

Dimension of a transistor has rapidly shrunk to increase the speed of device and to reduce the power consumption. However, it is accompanied with several problems like direct tunneling through the gate dioxide layer and low conductivity characteristic of poly-Si gate in nano-region. To cover these faults, study of new materials is urgently needed. Recently, high dielectric materials like $Al_2O_3$, $ZrO_2$, and $HfO_2$ are being studied for equivalent oxide thickness (EOT). However, poly-Si gate is not compatible with high-k materials for gate-insulator. Poly Si gate with high-k material has some problems such as gate depletion and dopant penetration problems. Therefore, new gate structure or materials that are compatible with high-k materials are also needed. TiN for metal/high-k gate stack is conductive enough to allow a good electrical connection and compatible with high-k materials. According to this trend, the study on dry etching of TiN for metal/high-k gate stack is needed. In this study, the investigations of the TiN etching characteristics were carried out using the inductively coupled $BCl_3$-based plasma system and adding $Cl_2$ gas. Dry etching of the TiN was studied by varying the etching parameters including $BCl_3$/Ar gas mixing ratio, RF power, DC-bias voltage to substrate, and $Cl_2$ gas addition. The plasmas were characterized by optical emission spectroscopy analysis. Scanning electron microscopy was used to investigate the etching profile.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.26 no.11
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• pp.816-820
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• 2013

We investigated the characteristics of the silicon oxy-nitride and nitride films grown by plasma-enhanced chemical vapor deposition (PECVD) at the low temperature with a varying $NH_3/N_2O$ mixing ratio and a fixed $SiH_4$ flow rate. The deposition temperature was held at $150^{\circ}C$ which was the temperature compatible with the plastic substrate. The composition and bonding structure of the nitride films were investigated using Fourier transform infrared spectroscopy (FTIR) and X-ray photoelectron spectroscopy (XPS). Nitrogen richness was confirmed with increasing optical band gap and increasing dielectric constant with the higher $NH_3$ fraction. The leakage current density of the nitride films with a high NH3 fraction decreased from $8{\times}10^{-9}$ to $9{\times}10^{-11}(A/cm^2$ at 1.5 MV/cm). This results showed that the films had improved electrical properties and could be acceptable as a gate insulator for thin film transistors by deposited with variable $NH_3/N_2O$ mixing ratio.

• Journal of the Korean Vacuum Society
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• v.19 no.2
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• pp.141-147
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• 2010

In this study, high-k oxide films like $Al_2O_3$, $TiO_2$, $HfO_2$ were deposited on Si, $SiO_2$/Si, GaAs wafers, and then the thermal conductivity was measured by using thermo-reflectance method which utilizes the reflectance variation of the film surface produced by the periodic temperature variation. The result shows that high-k oxide films with 50 nm thickness have high thermal conductivity of 0.80~1.29 W/(mK). Therefore, effectively dissipate the heat generated in the electric circuit such as CMOS memory device, and the heat transfer changes according to the micro grain size.

• The Korean Journal of Ceramics
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• v.6 no.4
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• pp.348-353
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• 2000

The effects of MnO$_2$ and Fe$_2$O$_3$ on the piezoelectric properties of 0.05PMN-0.451PT-0.499PZ ceramics were investigated. The addition of MnO$_2$ increased mechanical quality factor (Q$_m$) but decreased the dielectric constant (K$^{T}_{33}$) and compliance (S$^{E}_{11}$) of the specimens. These results indicated that MnO$_2$ behaves as an acceptor in 0.05MN-0.451PT-0.499PZ ceramics. The electromecanical coupling coefficient (K$_P$) of 0.05PMN-0.451PT-0.499PZ ceramics slightly increased with the addition of MnO$_2$ however, the enhancement of $K_P$ was insignificant. A small amount of Fe$_2$O$_3$ was added to enhance the $K_P$ of the 0.05PMN-0.451PT-0.499PZ + 0.5 wt% MnO$_2$ ceramics. The addition of Fe$_2$O$_3$ largely increased $K_P$ through the increase of the K$^{T}_{33}$ and the polarization. The mechanical quality factor of the specimens decreased with the addition of Fe$_2$O$_3$however, the reduction was negligible.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.1
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• pp.8-11
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• 2019

In this paper, a Ku-band 50-W internally-matched power amplifier is designed and fabricated using a CGHV1J070D GaN HEMT from Wolfspeed. To obtain the same magnitudes and phases for the output signals of the unit transistor cells, which constitute a power transistor, a slit pattern and an asymmetric T-junction are used in the input and output matching circuits. The internally-matched power amplifier is fabricated on two different thin-film substrates with relative dielectric constants of 40 and 9.8, respectively, and is measured under pulsed conditions with a pulse period of $330{\mu}s$ and a duty cycle of 6%. The measured results show a maximum output power of 50~73 W, a drain efficiency of 35.4~46.4%, and a power gain of 4.5~6.5 dB from 16.2 to 16.8 GHz.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.10
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• pp.9-16
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• 1999

When the conventional IPD (inter-poly-dielctrics) layer with ONO(oxide-nitride-oxide) structure was used in the Flash EEPROM cell, its data retention characteristics were significanfly degraded because the top oxide of the ONO layer was etched off due to the cleaning process used in the gate oxidation process for the peripheral MOSFETs. When the IPD layer with the ONON(oxide-nitride-oxide-nitride) was used there, however, its data retention characteristics were much improved because the top nitride of the ONON layer protected the top oxide from being etched in the cleaning process. For the modelling of the data retention characteristics of the Flash EEPROM cell with the ONON IPD layer, the decrease of the threshold voltage cue to the charge loss during the bake was here given by the empirical relation ${\Delta}V_t\; = \;{\beta}t^me^{-ea/kT}$ and the values of the ${\beta}$=184.7, m=0.224, Ea=0.31 eV were obtained with the experimental measurements. The activation energy of 0.31eV implies that the decrease of the threshold voltage by the back was dur to the movement of the trapped electrons inside the inter-oxide nitride layer. On the other hand, the results of the computer simulation using the model were found to be well consistent with the results of the electrical measurements when the thermal budget of the bake was not high. However, the latter was larger then the former in the case of the high thermal budger, This seems to be due to the leakage current generated by the extraction of the electrons with the bake which were injected into the inter-oxide niride later and were trapped there during the programming, and played the role to prevent the leakage current. To prevent the generation of the leakage current, it is required that the inter-oxide nitride layer and the top oxide layer be made as thin and as thick as possible, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.3
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• pp.7-11
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• 2011

In this paper, we proposed a simple and high-yield printing process for source and drain electrodes of organic thin film transistor (OTFT). The surface energy of PVP (poly 4-vinylphenol) gate dielectric was decreased from 56 $mJ/m^2$ to 45 $mJ/m^2$ by adding fluoride of 3000ppm into it. Meanwhile the surface energy of source and drain (S/D) electrodes area on the PVP was increased to 87 $mJ/m^2$ by treating the areas, which was patterned by photolithography, with oxygen plasma, maximizing the surface energy difference from the other areas. A conductive polymer, G-PEDOT:PSS, was deposited on the S/D electrode areas by brushing painting process. With such a simple process we could obtain a high yield of above 90 % in $16{\times}16$ arrays of OTFTs. The performance of OTFTs with the fluoride-added PVP was similar to that of OTFTs with the ordinary PVP without fluoride, generating the mobility of 0.1 $cm^2/V.sec$, which was sufficient enough to drive electrophoretic display (EPD) sheet. The EPD panel employing the OTFT-backpane successfully demonstrated to display some patterns on it.