• Title/Summary/Keyword: Thin liquid film

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Triple Pull-Down Gate Driver Using Oxide TFTs (트리플 풀다운 산화물 박막트랜지스터 게이트 드라이버)

  • Kim, Ji-Sun;Park, Kee-Chan;Oh, Hwan-Sool
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.1
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    • pp.1-7
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    • 2012
  • We have developed a new gate driver circuit for liquid crystal displays using oxide thin-film transistors (TFTs). In the new gate driver, negative gate bias is applied to turn off the oxide TFTs because the oxide TFT occasionally has negative threshold voltage (VT). In addition, we employed three parallel pull-down TFTs that are turned on in turns to enhance the stability. SPICE simulation showed that the proposed circuit worked successfully covering the VT range of -3 V ~ +6 V And fabrication results confirmed stable operation of the new circuit using oxide TFTs.

Modelling of ZMR process for fabrication of SOI (SOI소자 제죠를 위한 ZMR공정의 모델링)

  • 왕종회;김도현
    • Journal of the Korean Crystal Growth and Crystal Technology
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    • v.5 no.2
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    • pp.100-108
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    • 1995
  • Heat transfer plays a critical role in determining interface location and shape in ZMR process, which is used for the fabrication of silicon - on - insulator structure. In this work, the two - dimensional pseudo - steady - state ZMR model has been developed that can simulate the heat transfer process during ZMR process. It contains the radiation, convection and conduction heat transfer and determines the interface shapes. Numerical solutions from the model include flow field in the molten zone, temperature field in the full SOl structure and the location of solid/liquid interface in the silicon thin film and silicon substrate. We examined the effects of the various system parameters on the temperature profiles and the interface shape.

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Development of a Tool for the Electrical Analysis and Design of TFT/LCD System Package (TFT/LCD 시스템 패키지 전기적 특성 분석 및 설계도구의 구현)

  • Yim, Ho-Nam;Jee, Yong
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.32A no.12
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    • pp.149-158
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    • 1995
  • This paper describes the development of a software tool LCD FRAME that may guide the analyzing process for the electrical characteristics and the design procedure for constructing the thin film transistor liquid crystal display(TFT/LCD) packages. LCD FRAME can analyze its electrical characteristics from the TFT/LCD system package configuration, and provide the design variables to meet the user's requirements. These analysis and design procedure can be done in real time according to the model at simplified package level of TFT/LCD. LCD_FRAME is an object-oriented expert system which considers package elements as objects. With this LCD_FRAME software tool, we analyzed the I-V characteristics of a-Si TFT and its signal distortion which has maximum 1.58 $\mu$s delay along the panel scan line of the package containing 480 ${\times}$ 240 pixels. We designed the package structure of maximum 6.35 $\mu$s signal delays and 3360 ${\times}$ 780 pixels, and as a result we showed that the proper structure of 20 $\mu$m scan line width, 60$\mu$m panel TFT gate width and 8 $\mu$m gate length. This LCD_FRAME software tool provides results of the analysis and the design in the form of input files of the SPICE program, text data files, and graphic charts.

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Self-Aligned Offset Poly-Si TFT using Photoresist reflow process (Photoresist reflow 공정을 이용한 자기정합 오프셋 poly-Si TFT)

  • Yoo, Juhn-Suk;Park, Cheol-Min;Min, Byung-Hyuk;Han, Min-Koo
    • Proceedings of the KIEE Conference
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    • 1996.07c
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    • pp.1582-1584
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    • 1996
  • The polycrystalline silicon thin film transistors (poly-Si TFT) are the most promising candidate for active matrix liquid crystal displays (AMLCD) for their high mobilities and current driving capabilities. The leakage current of the poly-Si TFT is much higher than that of the amorphous-Si TFT, thus larger storage capacitance is required which reduces the aperture ratio fur the pixel. The offset gated poly-Si TFTs have been widely investigated in order to reduce the leakage current. The conventional method for fabricating an offset device may require additional mask and photolithography process step, which is inapplicable for self-aligned source/drain ion implantation and rather cost inefficient. Due to mis-alignment, offset devices show asymmetric transfer characteristics as the source and drain are switched. We have proposed and fabricated a new offset poly-Si TFT by applying photoresist reflow process. The new method does not require an additional mask step and self-aligned ion implantation is applied, thus precise offset length can be defined and source/drain symmetric transfer characteristics are achieved.

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A STUDY ON FLOW IN A SLIT NOZZLE FOR DISPENSING A LOW-VISCOSITY SOLUTION OF SINGLE-WALLED CARBON NANOTUBES (저점성 SWNT 분산액 도포용 슬릿 노즐 설계를 위한 유동해석)

  • Shon, B.C;Kwak, H.S.;Lee, S.H.
    • Journal of computational fluids engineering
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    • v.14 no.1
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    • pp.78-85
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    • 2009
  • A combined theoretical and numerical study is conducted to design a slit nozzle for large-area liquid coating. The objectives are to guarantee the uniformity in the injected flow and to provide the capability of explicit control of flow rate. The woking fluid is a dilute aqueous solution containing single-walled carbon nanotubes and its low viscosity and the presence of dispersed materials pose technical hurdles. A theoretical analysis leads to a guideline for the geometric design of a slit nozzle. The CFD-based numerical experiment is employed as a verification tool. A new flow passage unit, connected to the nozzle chamber, is proposed to permit the control of flow rate by using the commodity pressurizer. The numerical results confirm the feasibility of this idea. The optimal geometry of internal structure of the nozzle has been searched for numerically and the related issues are discussed.

Development of Process and Equipment for Roll-to-Roll convergence printing technology

  • Kim, Dong-Su;Bae, Seong-U;Kim, Chung-Hwan
    • Proceedings of the Materials Research Society of Korea Conference
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    • 2010.05a
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    • pp.19.1-19.1
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    • 2010
  • The process of manufacturing printed electronics using printing technology is attracting attention because its process cost is lower than that of the conventional semiconductor process. This technology, which offers both a lower cost and higher productivity, can be applied in the production of organic TFT (thin film transistor), solar cell, RFID(radio frequency identification) tag, printed battery, E-paper, touch screen panel, black matrix for LCD(liquid crystal display), flexible display, and so forth. In general, in order to implement printed electronics, narrow width and gap printing, registration of multi-layer printing by several printing units, and printing accuracy of under $20\;{\mu}m$ are all required. These electronic products require high precision to the degree of tens of microns - in a large area with flexible material, and mass productivity at low cost. As such, the roll-to-roll printing process is attracting attention as a mass production system for these printed electronic devices. For the commercialization of this process, two basic electronic ink technologies, such as conductive ink and polymers, and printing equipment have to be developed. Therefore, this paper addressed basis design and test to develop fine patterning equipment employing the roll-to-roll printing equipment and electronic ink.

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In-line Automatic Defect Repair System for TFT-LCD Production

  • Arai, Takeshi;Nakasu, Nobuaki;Yoshimura, Kazushi;Edamura, Tadao
    • Journal of Information Display
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    • v.10 no.4
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    • pp.202-205
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    • 2009
  • An automated circuit repair system was developed for enhancing the yield of nondefective liquid crystal panels, focusing on the resist patterns on the circuit material layer of thin-film transistor (TFT) substrates prior to etching. The developed system has an advantage over the parallel conventional system: In the former, the repair conditions depend on the type of resist whereas in the latter, the repair parameters must be fine-tuned for each circuit material. The developed system consists of a resist pattern defect inspection system and a pattern repair system for short and open defects. The repair system performs fine corrections of abnormal areas of the resist pattern. The open-repair system is equipped with a syringe to dispense resist. To maintain a stable resist diameter, a thermal insulator was installed in the syringe system. As a result, the diameter of the dispensed resist became much more stable than when no thermal insulator was used. The resist diameter was kept within the target of $400{\pm}100{\mu}m$. Furthermore, a prototype system was constructed, and using a dummy pattern, it was confirmed that the system worked automatically and correctly.

Design of the Half-bridge inverter for driving CCFL using manufactured PAN-PZT piezoelectric transformer (PAN-PZT 압전변압기 제작과 CCFL 구동용 하프브리지 인버터 설계)

  • Han, Jae-Hyun;Lim, Young-Cheol;Yang, Seung-Hak;Kweon, Gie-Hyoun
    • Proceedings of the KIEE Conference
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    • 2002.11d
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    • pp.194-196
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    • 2002
  • 액정표시장치(LCD; Liquid Crystal Display)는 표현된 정보를 가시화하기 위해 램프의 백라이트가 필수적인데 대부분 부피가 작고 효율과 휘도특성이 좋은 냉음극 방전램프가 사용된다. 램프는 고압으로 구동되며 높은 전압을 얻기 위해 일반적으로 권선 변압기를 사용한다. 그러나 권선 변압기의 경우 자체의 철심이나 권선의 손실로 인하여 출력 효율의 한계가 있으며, 고압을 위해 감긴 코일은 부피를 크게 하며 무겁게 만든다 이를 해결하기 위해 변압기 자체 손실을 줄이고 소형화가 가능하며 높은 승압비을 가진 PAN-PZT계의 적층형 압전 변압기를 제작하였다. 또한 회로의 손실을 줄이기 위한 영전압 스위칭(ZVS; Zero Voltage Switching)과 그리고 LCD패널과 인버터의 불필요한 간섭현상(EMI; Electro-Magnetic Interference)을 줄일 수 있으며 소형화가 가능한 하프 브리지형 압전 인버터를 설계하였다.

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Optimal Design of a-Si TFT Array for Minimization of Data-line Capacitance and Its Implementation (데이터 배선 용량 최소화를 위한 비정질 실리콘 박막 트렌지스터 배열의 최적화 설계와 구현)

  • Kim, C.W.;Yoon, J.K.;Kim, S.Y.;Kim, J.H.
    • Journal of Biomedical Engineering Research
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    • v.29 no.5
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    • pp.392-399
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    • 2008
  • Thin-film transistor (TFT) arrays for an x-ray detector require quite different design concept from that of the conventional active-matrix liquid crystal devices (AM-LCDs). In this paper anew design of TFT array which uses only SiNx for passivation layer is described to meet the detector performance and the product availability simultaneously. For the purpose of optimizing the design parameters of the TFT array, a Spice simulation was performed. As a result, some parameters, such as the TFT width, the data line capacitance, and the storage capacitance, were able to be fixed. The other parameters were decided within a permissible range of the TFT process especially the photolithography process and the wet etch process. Then we adapted the TFT array which had been produced by the proposed design to our prototype model (FDXD-1417 and evaluated it clinically by comparing with a commercial model (EPEX, Hologic, Beford, USA). The results say that our prototype model is slightly better than EPEX system in chest PA images. So we can prove the technical usefulness and the commercial values of the proposed TFT design.

Sputtered ZTO as a blocking layer at conducting glass and $TiO_2$ Interfaces in Dye-Sensitized Solar Cells (GZO/ZTO 투명전극을 이용한 DSSC의 광전 변환 효율 특성)

  • Park, Jaeho;Lee, Kyungju;Song, Sangwoo;Jo, Seulki;Moon, Byungmoo
    • 한국신재생에너지학회:학술대회논문집
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    • 2011.11a
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    • pp.53.2-53.2
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    • 2011
  • Dye-sensitized solar cells(DSSCs) have been recognized as an alternative to the conventional p-n junction solar cells because of their simple fabrication process, low production cost, and transparency. A typical DSSC consists of a transparent conductive oxide (TCO) electrode, a dye-sensitized oxide semiconductor nanoparticle layer, liquid redox electrolyte, and a Pt-counter electrode. In dye-sensitized solar cells, charge recombination processes at interfaces between coducting glass, $TiO_2$, dye, and electrolyte play an important role in limiting the photon-to-electron conversion efficiency. A layer of ZTO thin film less than ~200nm in thickness, as a blocking layer, was deposited by DC magnetron sputtering method directly onto the anode electrode to be isolated from the electrolyte in dye-sensitized solar cells(DSCs). This is to prevent the electrons from back-transferring from the electrode to the electrolyte ($I^-/I_3^-$). The presented DSCs were fabricated with working electrode of Ga-doped ZnO glass coated with blocking ZTO layer, dye-attached nanoporous $TiO_2$ layer, gel electrolyte and counter electrode of Pt-deposited GZO glass. The effects of blocking layer were studied with respect to impedance and conversion efficiency of the cells.

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