• Proceedings of the KIEE Conference
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• 2000.11c
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• pp.452-454
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• 2000

In recent years, the Thin Film Transistor Liquid Crystal Display (TFT-LCD) is used in a variety of products as an interfacing device between human and them. Since TFT-LCDs have trend toward larger Panel sizes and higher spatial and/or gray-scale resolution, pixel charging characteristic is very important for the large panel size and high resolution TFT-LCD pixel characteristics. In this paper, both data line precharging method and line time extension (LiTEX) method is applied to Pixel Design Array Simulation Tool (PDAST) and the pixel charging characteristics of TFT-LCD array were simulated, which were compared with the results calculated by both PDAST In which the conventional device model of a-Si TFTs and gate step method is implemented.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.1
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• pp.79-84
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• 2004

A light-guide is one of several important components of backlight unit in TFT-LCD. The manufacturing technology and optical system design of the light guide is very sensitive to quality and cost of the TFT-LCD module. In the present study a new manufacturing method which is called as direct surface forming(DSF) has been tested under various conditions. DSF is very similar to the well-known hot embossing except for partial contact between mold and substrate. The final V-groove pattern shows different shapes depend on the temperature of mold surface, contact time of mold and depth of V-groove.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.557-560
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• 1999

The design of large area thin film transistor liquid crystal displays (TFT-LCDs) requires consideration of cross-talks between the data lines and pixel electrodes. These limits are imposed by the parasitic capacitive elements present in a pixel. The capacitive coupling of the data line signal onto the pixel causes a pixel voltage error. In this study semi-empirical capacitance model which is adopted from VLSI interconnection capacitance calculations was used to calculate mutual coupling capacitances. With calculated mutual coupling capacitances and given image pattern, the root mean square(RMS) voltage of pixel is calculated to see vertical cross-talk from the first to the last column. The information obtained from this study could be utilized to design the larger area and finer image quality panel.

• Proceedings of the KIPE Conference
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• 2002.11a
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• pp.147-151
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• 2002

액정표시장치(LCD; Liquid Crystal Display)는 표현된 정보를 가시화하기 위해 램프의 백라이트가 필수적인데 대부분 부피가 작고 효율과 휘도특성이 좋은 냉음극 방전램프가 사용된다. 램프는 고압으로 구동되며 높은 전압을 얻기 위해 일반적으로 권선 변압기를 사용한다 그러나 권선 변압기의 경우 자체의 철심이나 권선의 손실로 인하여 출력 효율의 한계가 있으며, 고압을 위해 감긴 코일은 부피를 크게 하며 무겁게 만든다. 이를 해결하기 위해 본 논문에서는 변압기 자체 손실을 줄이고 소형화가 가능하며 높은 승압비을 가진 PAN-PZT계의 적층형 압전 변압기를 제작하였으며, 회로의 손실을 줄이기 위한 영전압 스위칭(ZVS; Zero Voltage Switching)과 그리고 LCD패널과 인버터의 불필요한 간섭현상(EMI; Electro-Magnetic Interference)을 줄일 수 있으며 소형화가 가능한 풀 브리지형 압전 인버터를 설계하였다.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.47-47
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• 2007

Indium oxide conducting films were dep9sited on Si(100) substrates at various temperatures by liquid delivery metal organic chemical vapor deposition using Indium (III) tris (2,2,6,6-tetramethyl-3.5-heptanedionato) $(dpm)_3$ precursors. The films deposited at $200{\sim}400^{\circ}C$ were grown with a (111) preferred orientation and exhibit an increase of grain size from 21 to 33nm with increasing deposition temperature. In the range of deposition temperature, there is no metallic indium phase in deposited films.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1864-1865
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• 2007

In this paper, we proposed pre-filter algorithms which using frequency domain analysis method, for the detections of defects in large-sized Thin Film Transistor-Liquid Crystal Display(TFT-LCD) panel surfaces. We performed frequency analysis with 1-D, 2-D FFT methods for extract periodic patterns of lattice structures in TFT-LCDs. To remove this patterns, band-stop filters were used for eliminating specific frequency components. In order to acquire only defected images, we used 2-D inverse FFT methods which can be reverts images that remains defects.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.07a
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• pp.320-323
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• 2000

In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2005.07a
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• pp.585-586
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• 2005

BSCCO thin films were fabricated by an ion beam sputtering method with an ultra-low growth rate, and sticking coefficients of the respective elements are evaluated. The sticking coefficient of Bi element in BSCCO film formation was observed to show a unique temperature dependence; it was almost a constant value of 0.49 below about $730^{\circ}C$ and decreased linearly over about $730^{\circ}C$. In contrast, Sr and Ca, displayed no such remarkable temperature dependence. This behavior of the sticking coefficient was explained consistently on the basis of the evaporation and sublimation processes of Bi2O3. It is considered that the liquid phase of the bismuth oxide plays an important role in the Bi 2212 phase formation in the co-deposition process.

• Journal of Sensor Science and Technology
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• v.32 no.4
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• pp.252-256
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• 2023

A one-step method for nanoscale patterning of silver ionic ink on a substrate is developed using a microscale, elastic mold deformation. This method yields unique micro/nanoscale metallic structures that differ from those produced using the original molds. The linewidth of these metallic structures is significantly reduced (approximately 10 times) through the sidewall deformation of the original mold cavity on a thin liquid film, as verified by finite element analysis. The process facilitates the fabrication of various, isolated and complex micro/nanoscale metallic structures with negligible residual layers at low cost and high throughput. These structures can be utilized for various applications, including optoelectronics, wearable sensors, and metaverse-related devices. Our approach offers a promising tool for manipulation and fabrication of micro/nanoscale structures of various functional materials.

• Nuclear Engineering and Technology
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• v.27 no.4
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• pp.503-517
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• 1995

A mechanistic model for forced convective transition boiling has been developed to predict transition boiling heat flux realistically. This model is based on a postulated multi­stage boiling process occurring during the passage time of an elongated vapor blanket specified at a critical heat flux condition. Between the departure from nucleate boiling (DNB) and the departure from film boiling (DFB) points, the boiling heat transfer is established through three boiling stages, namely, the macrolayer evaporation and dryout governed by nucleate boiling in a thin liquid film and the unstable film boiling. The total heat transfer rate during the transition boiling is the sum of the heat transfer rates after the DNB weighted by the time fractions of each stage, which are defined as the ratio of each stage duration to the vapor blanket passage time. The model predictions are compared with some available experimental transition boiling data. From these comparisons, it can be seen that the transition boiling heat fluxes including the maximum heat flux and the minimum film boiling heat flux are nil predicted at low qualities/high pressures near 10 bar.