• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.453-458
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• 1987

Amorphous silicon thin-film transtors (TFT's) have been designed and fabricated on glass substrates. The hydrogenated amorphous silicon (a-Si:H) thin-film has been deposited by decomposing silane(SiH4) in hydorgen ambient by rf glow discharge method. Amorphous silicon nitride(a-Si:H) has been chosen as the gate dielectric material. It has been prepared by decomposing the mixed gas of silane(SiH4) and ammonia(NH3). The electrical properties and performance characteristics of the thin-film transistrs have been measured and compared with the requirements for the switching elements in liquid crystal flat panel display. The results show that liquid crystal flat panel displays can be fabricated using the thin-film transistors described in this paper.

• Journal of the Semiconductor & Display Technology
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• v.2 no.4
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• pp.31-35
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• 2003

We present a formation technique of thin film heater for heat transfer components. Thin film structures of Cr-Si have been prepared on top of alumina substrates by magnetron sputtering. More samples of Mo thin films were prepared on silicon oxide and silicon nitride substrates by electron beam evaporation technology. The electrical properties of the thin film structures were measured up to the temperature of $500^{\circ}C$. The thickness of the thin films was ranged to about 1 um, and a post annealing up to $900^{\circ}C$ was carried out to achieve more reliable film structures. In measurements of temperature coefficient of resistance (TCR), chrome-rich films show the metallic properties; whereas silicon-rich films do the semiconductor properties. Optimal composition between Cr and Si was obtained as 1 : 2, and there is 20% change or less of surface resistance from room temperature to $500^{\circ}C$. Scanning electron microscopy (SEM) and Auger electron spectroscopy (AES) were used for the material analysis of the thin films.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.52-52
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• 2011

A novel deposition process for n-type nanocrystalline silicon (n-type nc-Si) thin films at room temperature has been developed by adopting the neutral beam assisted chemical vapor deposition (NBa-CVD). During formation of n-type nc-Si thin film by the NBa-CVD process with silicon reflector electrode at room temperature, the energetic particles could induce enhance doping efficiency and crystalline phase in polymorphous-Si thin films without additional heating on substrate; The dark conductivity and substrate temperature of P-doped polymorphous~nano crystalline silicon thin films increased with increasing the reflector bias. The NB energy heating substrate(but lower than $80^{\circ}C$ and increase doping efficiency. This low temperature processed doped nano-crystalline can address key problem in applications from flexible display backplane thin film transistor to flexible solar cell.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.65 no.10
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• pp.1702-1705
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• 2016

We propose a novel hydrogen-reduced p-type amorphous silicon oxide buffer layer between $TiO_2$ antireflection layer and p-type silicon window layer of silicon thin film solar cells. This new buffer layer can protect underlying the $TiO_2$ by suppressing hydrogen plasma, which could be made by excluding $H_2$ gas introduction during plasma deposition. Amorphous silicon oxide thin film solar cells with employing the new buffer layer exhibited better conversion efficiency (8.10 %) compared with the standard cell (7.88 %) without the buffer layer. This new buffer layer can be processed in the same p-chamber with in-situ mode before depositing main p-type amorphous silicon oxide window layer. Comparing with state-of-the-art buffer layer of AZO/p-nc-SiOx:H, our new buffer layer can be processed with cost-effective, much simple process based on similar device performances.

• The Korean Journal of Ceramics
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• v.3 no.1
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• pp.13-17
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• 1997

It is identified that the diamond films grown o bias-treated (100) silicon showed different surface morphologies and film textures according to the initial applied dc bias voltage at the same growth condition. The highly oriented diamond film (HODF) was successfully grown on -200 V bias-treated silicon substrate in which the heteroepitaxial relation of $(100)_{dimond}//(100)_{si}\; and\; [110]_{diamond}//[110]_{si}$ was identified. On the contrary, the heteroepitaxial relation was considerably disturbed in the samples bias-voltage was a key factor in growing the highly oriented diamond film on (100) silicon substrate. Considering the experimental results, we proposed a new model about heteroepitaxial diamond growth on silicon, in which 9 diamond unit cell are matched with 4 silicon cells and the bond covalency of both atoms is satisfied via the intermediate layer at the interface as well.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.1455-1458
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• 2008

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) are fabricated on flexible organic polymer foil substrates. As-fabricated performance, electrical bias-stability at elevated temperatures, electrical response under mechanical flexing, and prolonged mechanical stability of the TFTs are studied. TFTs made on plastic at ultra low process temperatures of $150^{\circ}C$ show initial electrical performance like TFTs made on glass but large gate-bias stress instability. An abnormal saturation of the instability against operation temperature is observed.

• Current Photovoltaic Research
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• v.6 no.2
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• pp.31-38
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• 2018

Multijunction solar cells present a practical solution towards a better photovoltaic conversion for a wider spectral range. In this review, we compare different types of multi-ijunction solar cell. First, we introduce thin film multijunction solar cell include to the thin film silicon, III-V material and chalcopyrite material. Until now the maximum reported power conversion efficiencies (PCE) of solar cells having different component sub-cells are 14.0% (thin film silicon), 46% (III-V material), 4.4% (chalcopyrite material) respectively. We then discuss the development of multijunction solar cell in which c-Si is used as bottom sub-cell while III-V material, thin film silicon, chalcopyrite material or perovskite material is used as top sub-cells.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.313-313
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• 2013

For high-performance TFT (Thin film transistor), poly-crystalline semiconductor thin film with low resistivity and high hall carrier mobility is necessary. But, conventional SPC (Solid phase crystallization) process has disadvantages in fabrication such as long annealing time in high temperature or using very expensive Excimer laser. On the contrary, MIC (Metal-induced crystallization) process enables semiconductor thin film crystallization at lower temperature in short annealing time. But, it has been known that the poly-crystalline semiconductor thin film fabricated by MIC methods, has low hall mobility due to the residual metals after crystallization process. In this study, Ni metal was shallow implanted using PIII&D (Plasma Immersion Ion Implantation & Deposition) technique instead of depositing Ni layer to reduce the Ni contamination after annealing. In addition, the effect of external magnetic field during annealing was studied to enhance the amorphous silicon thin film crystallization process. Various thin film analytical techniques such as XRD (X-Ray Diffraction), Raman spectroscopy, and XPS (X-ray Photoelectron Spectroscopy), Hall mobility measurement system were used to investigate the structure and composition of silicon thin film samples.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.145-148
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• 2001

In this paper, polycrystalline silicon thin film transistor using by Solid Phase Crystallization(SPC) were fabricated, and these devices were measured and analyzed the electrical output and transfer characteristics along to DC voltage stress. The transfer characteristics of polycrystalline silicon thin film transistor depended on drain and gate voltages. Threshold voltage is high with long channel length and narrow channel width. And output characteristics of polycrystalline silicon thin film transistor flowed abruptly much higher drain current. The devices induced electrical stress are decreased drain current. At last, field effect mobility is the faster as channel length is high and channel width is narrow.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.5
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• pp.364-369
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• 2011

Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.