• KSTLE International Journal
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• v.6 no.2
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• pp.33-38
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• 2005

Submicron-scale patterns made of polymethyl methacrylate (PMMA) were fabricated on silicon-wafer using a capillarity-directed soft lithographic technique. Polyurethane acrylate (PUA) stamps (Master molds) were used to fabricate the patterns. Patterns with three different aspect ratios were fabricated by varying the holding time. The patterns fabricated were the negative replica of the master mold. The patterns so obtained were investigated for their adhesion and friction properties at nano-scale using AFM. Friction tests were conducted in the range of 0-80 nN. Glass (Borosilicate) balls of diameter 1.25 mm mounted on cantilever (Contact Mode type NPS) were used as tips. Further, micro-friction tests were performed using a ball-on-flat type micro-tribe tester, under reciprocating motion, using a soda lime ball (1 mm diameter) under a normal load of 3,000 mN. All experiments were conducted at ambient temperature ($24{\pm}1^{\circ}C$) and relative humidity ($45{\pm}5\%$). Results showed that the patterned samples exhibited superior tribological properties when compared to the silicon wafer and non-patterned sample (PMMA thin film) both at the nano and micro-scales, owing to their increased hydrophobicity and reduced real area of contact. In the case of patterns it was observed that their morphology (shape factor and size factor) was decisive in defining the real area of contact.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.9
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• pp.1615-1622
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• 2008

We have fabricated the poly-silicon thin film transistor(TFT) which has the LDD-region with graded spacer. The devices of n-channel poly-si TFT's hydrogenated by $H_2$ and $H_2$/plasma processes were fabricated for the devices reliability. We have biased the devices under the gate voltage stress conditions of maximum leakage current. The parametric characteristics caused by gate voltage stress conditions in hydrogenated devices are investigated by measuring/analyzing the drain current, leakage current, threshold voltage($V_{th}$), sub-threshold slope(S) and transconductance($G_m$) values. As a analyzed results of characteristics parameters, the degradation characteristics in hydrogenated n-channel polysilicon TFT's are mainly caused by the enhancement of dangling bonds at the poly-Si/$SiO_2$ interface and the poly-Si grain boundary due to dissolution of Si-H bonds. The structure of novel proposed poly-Si TFT's are the simplicities of the fabrication process steps and the decrease of leakage current by reduced lateral electric field near the drain region.

• Journal of the Korean institute of surface engineering
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• v.54 no.5
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• pp.230-237
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• 2021

In this study, the influence of silicon contents on the microstructure, mechanical and tribological properties of Ti-Al-Si-N coatings were systematically investigated for application of cutting tools. The composition of the Ti-Al-Si-N coatings were controlled by different combinations of TiAl₂ and Ti₄Si composite target powers using an arc ion plating technique in a reactive gas mixture of high purity Ar and N₂ during depositions. Ti-Al-Si-N films were nanocomposite consisting of nanosized (Ti,Al,Si)N crystallites embedded in an amorphous Si₃N₄/SiO₂ matrix. The instrumental analyses revealed that the synthesized Ti-Al-Si-N film with Si content of 5.63 at.% was a nanocomposites consisting of nano-sized crystallites (5-7 nm in dia.) and a three dimensional thin layer of amorphous Si₃N₄ phase. The hardness of the Ti-Al-Si-N coatings also exhibited the maximum hardness value of about 47 GPa at a silicon content of ~5.63 at.% due to the microstructural change to a nanocomposite as well as the solid-solution hardening. The coating has a low friction coefficient of 0.55 at room temperature against an Inconel alloy ball. These excellent mechanical and tribological properties of the Ti-Al-Si-N coatings could help to improve the performance of machining and cutting tool applications.

• Korean Journal of Metals and Materials
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• v.50 no.8
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• pp.613-618
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• 2012

We report on electrical and mechanical properties of silicon nitride ($SiN_x$) films deposited by a plasma enhanced chemical vapor deposition (PECVD) method at $200^{\circ}C$ from $SiH_4$ highly diluted in $N_2$. The films were also prepared from $SiH_4$ diluted in He for comparison. The $N_2$ dilution was also effective in improving adhesion of the $SiN_x$ films, fascilitating construction of thin film transistors (TFTs). Metal-insulator-semiconductor (MIS) and Metal-insulator-Metal (MIM) structures were used for capacitance-voltage (C-V) and current-voltage (I-V) measurements, respectively. The resistivity and breakdown field strength of the $SiN_x$ films from $N_2$-diluted $SiH_4$ were estimated to be $1{\times}10^{13}{\Omega}{\cdot}cm$, 7.4 MV/cm, respectively. The MIS device showed a hysteresis window and a flat band voltage shift of 3 V and 0.5 V, respectively. The TFTs fabricated by using these films showed a field-effect mobility of $0.16cm^2/Vs$, a threshold voltage of 3 V, a subthreshold slope of 1.2 V/dec, and an on/off ratio of > $10^6$.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.43-49
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• 2000

The TiN thin films were deposited by ALE(atomic layer epitaxy) on (100) silicon substrate. The TiN thin films were characterized by means of XRD, 4-point probe, AFM, AES and SEM. TEMAT(terakis(ethyl methy lamino)titanium) and $NH_3$ were injected into the reactor in sequence of TEMAT-$N_2-NH_3-N_2$ to ensure a saturated surface reaction. As a result, the depostion rate of the TiN film was controlled by self-limiting growth mechanism at temperature range form 150 to 220 $^{\circ}C$. Deposited TiN films, all of which show amorphous structure, had a fixed deposition rate of 4.5 ${\AA}$/cycle. The resistivity of 210 ~ 230 ${\mu}{\Omega}{\cdot}$cm and the surface r.m.s. roughness of 7.9 ~ 9.3 ${\AA}$ were measured. When TiN film of 2000 ${\AA}$ were deposited, a excellent step coverage were observed in a trench structure of 0.43${\mu}m$ contacts with 6:1 aspect ratio.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.267-267
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• 1998

The fluorine doped silicon oxide (SiOF) intermetal dielectric (IMD) films have been of interest due to their lower dielectric constant and compatibility with existing process tools. However instability issues related to bond and increasing dielectric constant to water absorption when the SiOF films was exposured to atmospheric ambient. Therefore, the purpose of this research is to study the effect of post oxygen plasma treatment on the resistance of moisture absorption and reliability of SiOF film. Improvement of moisture absorption resistance of SiOF film is due to the forming of thin SiO₂layer at the SiOF film surface. It is thought that the main effect of the improvement of moisture absorption resistance was densification of the top layer and reduction in the number of Si-F bonds that tend to associate with OH bonds. However, the dielectric constant was increased when plasma treatment time is above 5 min. In this study, therefore, it is thought that the proper plasma treatment time is 3 min when plasma treatment condition is 700 W of microwave power, 3 mTorr of process pressure and 300℃ of substrate temperature.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.434-435
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• 2012

Plasma enhanced chemical vapor deposition (PECVD) silicon dioxide thin films have many applications in semiconductor manufacturing such as inter-level dielectric and gate dielectric metal oxide semiconductor field effect transistors (MOSFETs). Fundamental chemical reaction for the formation of SiO2 includes SiH4 and O2, but mixture of SiH4 and N2O is preferable because of lower hydrogen concentration in the deposited film [1]. It is also known that binding energy of N-N is higher than that of N-O, so the particle generation by molecular reaction can be reduced by reducing reactive nitrogen during the deposition process. However, nitrous oxide (N2O) gives rise to nitric oxide (NO) on reaction with oxygen atoms, which in turn reacts with ozone. NO became a greenhouse gas which is naturally occurred regulating of stratospheric ozone. In fact, it takes global warming effect about 300 times higher than carbon dioxide (CO2). Industries regard that N2O is inevitable for their device fabrication; however, it is worthwhile to develop a marginable nitrous oxide free process for university lab classes considering educational and environmental purpose. In this paper, we developed environmental friendly and material cost efficient SiO2 deposition process by substituting N2O with O2 targeting university hands-on laboratory course. Experiment was performed by two level statistical design of experiment (DOE) with three process parameters including RF power, susceptor temperature, and oxygen gas flow. Responses of interests to optimize the process were deposition rate, film uniformity, surface roughness, and electrical dielectric property. We observed some power like particle formation on wafer in some experiment, and we postulate that the thermal and electrical energy to dissociate gas molecule was relatively lower than other runs. However, we were able to find a marginable process region with less than 3% uniformity requirement in our process optimization goal. Surface roughness measured by atomic force microscopy (AFM) presented some evidence of the agglomeration of silane related particles, and the result was still satisfactory for the purpose of this research. This newly developed SiO2 deposition process is currently under verification with repeated experimental run on 4 inches wafer, and it will be adopted to Semiconductor Material and Process course offered in the Department of Electronic Engineering at Myongji University from spring semester in 2012.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.3
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• pp.33-38
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• 2021

Recently, rollable and foldable displays are attracting great attention in the flexible display market due to their excellent form factor. To predict and prevent the mechanical failure of the display panels, it is essential to accurately understand the mechanical properties of brittle SiN_x thin films, which have been used as an insulating film in flexible displays. In this study, tensile properties of the ~130 nm- and ~320 nm-thick SiN_x thin films were successfully measured by coating a ~190 nm-thick organic nano-support-layer (PMMA, PS, P3HT) on the fragile SiN_x thin films and stretching the films as a bilayer state. Young's modulus values of the ~130 nm and ~320 nm SiN_x thin films fabricated through the controlled chamber pressure and deposition power (A: 1250 mTorr, 450 W/B: 1000 mTorr, 600 W/C: 750 mTorr, 700 W) were calculated as A: 76.6±3.5, B: 85.8±4.6, C: 117.4±6.5 GPa and A: 100.1±12.9, B: 117.9±9.7, C: 159.6 GPa, respectively. As a result, Young's modulus of ~320 nm SiN_x thin films fabricated through the same deposition condition increased compared to the ~130 nm SiN_x thin films. The tensile testing method using the organic nano-support-layer was effective in the precise measurement of the mechanical properties of the brittle thin films. The method developed in this study can contribute to the robust design of the rollable and foldable displays by enabling quantitative measurement of mechanical properties of fragile thin films for flexible displays.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2009.11a
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• pp.65-65
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• 2009

High temperature silicon carbide Schottky diode was fabricated with Au deposited on poly 3C-SiC thin film grown on p-type Si(100) using atmospheric pressure chemical vapor deposition. The charge transport mechanism of the diode was studied in the temperature range of 300 K to 550 K. The forward and reverse bias currents of the diode increase strongly with temperature and diode shows a non-ideal behavior due to the series resistance and the interface states associated with 3C-SiC. The charge transport mechanism is a temperature activated process, in which, the electrons passes over of the low barriers and in turn, diode has a large ideality factor. The charge transport mechanism of the diode was analyzed by a Gaussian distribution of the Schottky barrier heights due to the Schottky barrier inhomogeneities at the metal-semiconductor interface and the mean barrier height and zero-bias standard deviation values for the diode was found to be 1.82 eV and $s_0$=0.233 V, respectively. The interface state density of the diode was determined using conductance-frequency and it was of order of $9.18{\times}10^{10}eV^{-1}cm^{-2}$.