• 제목/요약/키워드: Thin Film Patterning Process

검색결과 86건 처리시간 0.031초

공정 조건에 따른 비정질 탄소막 표면 물성분석 (Surface Properties of ACL Thin Films Depending on Process Conditions)

  • 김광표;최정은;홍상진
    • 반도체디스플레이기술학회지
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    • 제18권2호
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    • pp.44-47
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    • 2019
  • Amorphous carbon layer (ACL) is actively used as an etch mask. Recent advances in patterning ACL requires the next level of durability of hard mask in high aspect ratio etch in near future semiconductor manufacturing, and it is worthwhile to know the surface property of ACL thin film to enhance the property of etch hard mask. In this research, ACL are deposited by 6 inch plasma enhanced chemical vapor deposition system with $C_3H_6$ and $N_2$ gas mixture. Surface properties of deposited ACL are investigated depending on gas flow, pressure, RF power. Fourier transform infrared is used for the analysis of surface chemistry, and X-ray photoemission spectra is used for the structural analysis with the consideration of the contents of $sp^2$ and $sp^3$ through fitting of C1s. Also mechanical properties of deposited ACL are measured in order to evaluate hardness.

모세관 리소그라피를 이용한 고종횡비 나노구조 형성법 (Capillary-driven Rigiflex Lithography for Fabricating High Aspect-Ratio Polymer Nanostructures)

  • 정훈의;이성훈;김필남;서갑양
    • 한국가시화정보학회지
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    • 제5권1호
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    • pp.3-8
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    • 2007
  • We present simple methods for fabricating high aspect-ratio polymer nanostructures on a solid substrate by rigiflex lithography with tailored capillarity and adhesive force. In the first method, a thin, thermoplastic polymer film was prepared by spin coating on a substrate and the temperature was raised above the polymer's glass transition temperature ($T_g$) while in conformal contact with a poly(urethane acrylate) (PUA) mold having nano-cavities. Consequently, capillarity forces the polymer film to rise into the void space of the mold, resulting in nanostructures with an aspect ratio of ${\sim}4$. In the second method, very high aspect-ratio (>20) nanohairs were fabricated by elongating the pre-formed nanostructures upon removal of the mold with the aid of tailored capillarity and adhesive force at the mold/polymer interface. Finally, these two methods were further used to fabricate micro/nano hierarchical structures by sequential application of the molding process for mimicking nature's functional surfaces such as a lotus leaf and gecko foot hairs.

패턴된 GaN 에피층 위에 ZnO 막대의 수직성장 (Growth of vertically aligned Zinc Oxide rod array on patterned Gallium Nitride epitaxial layer)

  • 최승규;이성학;장재민;김정아;정우광
    • 한국재료학회지
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    • 제17권5호
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    • pp.273-277
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    • 2007
  • Vertically aligned Zinc Oxide rod arrays were grown by the self-assembly hydrothermal process on the GaN epitaxial layer which has a same lattice structure with ZnO. Zinc nitrate and DETA solutions are used in the hydrothermal process. The $(HfO_2)$ thin film was deposited on GaN and the patterning was made by the photolithography technique. The selective growth of ZnO rod was achieved with the patterned GaN substrate. The fabricated ZnO rods are single crystal, and have grown along hexagonal c-axis direction of (002) which is the same growth orientation of GaN epitaxial layer. The density and the size of ZnO rod can be controlled by the pattern. The optical property of ordered array of vertical ZnO rods will be discussed in the present work.

박막트랜지스터의 습식 및 건식 식각 공정 (The Wet and Dry Etching Process of Thin Film Transistor)

  • 박춘식;허창우
    • 한국정보통신학회논문지
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    • 제13권7호
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    • pp.1393-1398
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    • 2009
  • 본 연구는 LCD용 비정질 실리콘박막트랜지스터의 제조공정중 가장 중요한 식각 공정에서 각 박막의 특성에 맞는 습식 및 건식식각공정을 개발하여 소자의 특성을 안정시키고자 한다. 본 연구의 수소화 된 비정질 실리콘 박막 트랜지스터는 Inverted Staggered 형태로 게이트 전극이 하부에 있다. 실험 방법은 게이트전극, 절연층, 전도층, 에치스토퍼 및 포토레지스터층을 연속 증착한다. 스토퍼층을 게이트 전극의 패턴으로 남기고, 그 위에 n+a-Si:H 층 및 NPR(Negative Photo Resister)을 형성시킨다. 상부 게이트 전극과 반대의 패턴으로 NPR층을 패터닝하여 그것을 마스크로 상부 n+a-Si:H 층을 식각하고, 남아있는 NPR층을 제거 한다. 그 위 에 Cr층을 증착한 후 패터닝 하여 소오스-드레인 전극을 위한 Cr층을 형성시켜 박막 트랜지스터를 제조한다. 여기서 각 박막의 패터닝은 식각 공정으로 각단위 박막의 특성에 맞는 건식 및 습식식각 공정이 필요하다. 제조한 박막 트랜지스터에서 가장 흔히 발생되는 문제는 주로 식각 공정시 over 및 under etching 이며, 정확한 식각을 위하여 각 박막에 맞는 식각공정을 개발하여 소자의 최적 특성을 제공하고자한다. 이와 같이 공정에 보다 엄격한 기준의 건식 및 습식식각 공정 그리고 세척 등의 처리공정을 정밀하게 실시하여 소자의 특성을 확실히 개선 할 수 있었다.

근접장현미경을 이용한 폴리머박막 나노리쏘그라피 공정의 특성분석 (Characteristics of Nanolithography Process on Polymer Thin-film using Near-field Scanning Optical Microscope)

  • 권상진;김필규;장원석;정성호
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2004년도 추계학술대회 논문집
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    • pp.590-595
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    • 2004
  • The shape and size variations of the nanopatterns produced on a positive photoresist using a near-field scanning optical microscope(NSOM) are investigated with respect to the process variables. A cantilever type nanoprobe having a 100nm aperture at the apex of the pyramidal tip is used with the NSOM and a He-Cd laser at a wavelength of 442nm as the illumination source. Patterning characteristics are examined for different laser beam power at the entrance side of the aperture( $P_{in}$ ), scan speed of the piezo stage(V), repeated scanning over the same pattern, and operation modes of the NSOM(DC and AC modes). The pattern size remained almost the same for equal linear energy density. Pattern size decreased for lower laser beam power and greater scan speed, leading to a minimum pattern width of around 50nm at $P_{in}$ =1.2$\mu$W and V=12$\mu$m/. Direct writing of an arbitrary pattern with a line width of about 150nm was demonstrated to verify the feasibility of this technique for nanomask fabrication. Application on high-density data storage using azopolymer is discussed at the end.

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미세접촉프린팅 공정을 이용한 유연성 유기박막소자(OTFT)설계 및 제작 (Design and Fabrication of Flexible OTFTs by using Nanocantact Printing Process)

  • 조정대;김광영;이응숙;최병오
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 2005년도 추계학술대회 논문집
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    • pp.506-508
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    • 2005
  • In general, organic TFTs are comprised of four components: gate electrode, gate dielectric, organic active semiconductor layer, and source and drain contacts. The TFT current, in turn, is typically determined by channel length and width, carrier field effect mobility, gate dielectric thickness and permittivity, contact resistance, and biasing conditions. More recently, a number of techniques and processes have been introduced to the fabrication of OTFT circuits and displays that aim specifically at reduced fabrication cost. These include microcontact printing for the patterning of metals and dielectrics, the use of photochemically patterned insulating and conducting films, and inkjet printing for the selective deposition of contacts and interconnect pattern. In the fabrication of organic TFTs, microcontact printing has been used to pattern gate electrodes, gate dielectrics, and source and drain contacts with sufficient yield to allow the fabrication of transistors. We were fabricated a pentacene OTFTs on flexible PEN film. Au/Cr was used for the gate electrode, parylene-c was deposited as the gate dielectric, and Au/Cr was chosen for the source and drain contacts; were all deposited by ion-beam sputtering and patterned by microcontact printing and lift-off process. Prior to the deposition of the organic active layer, the gate dielectric surface was treated with octadecyltrichlorosilane(OTS) from the vapor phase. To complete the device, pentacene was deposited by thermal evaporation and patterned using a parylene-c layer. The device was shown that the carrier field effect mobility, the threshold voltage, the subthreshold slope, and the on/off current ratio were improved.

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금속 패터닝과 Blank노광을 이용한 감광성 유리의 미세가공 (Microfabrication of Photosensitive Glass Using Metal Patterning and Blank Exposure)

  • 조재승;강형범;윤혜진;김효진;임현우;조시형;임실묵
    • 한국표면공학회지
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    • 제46권3호
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    • pp.99-104
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    • 2013
  • The simple and cost-effective microfabrication method of photosensitive glass (PSG) using metal patterning and blank exposure was proposed. Conventional photolithography for micromachining of PSG needs a costly quartz mask which has high transmittance as an optical property. However, in this study the process was improved through the combination of micro-patterned Ti thin film and blank UV exposure without quartz mask. The effect of UV exposure time as well as the DHF etching condition was investigated. UV exposure test was performed within the range from 3 min to 9 min. The color and etch result of PSG exposed for 5 min were the most clear and effective to etch more precisely, respectively. The etching results of PSG in diluted hydrofluoric acid (DHF) with a concentration of 5, 10, 15 vol% were compared. The effect on the side etch was insignificant while the etch rate was proportional as the concentration increased. 10 vol% DHF results not only high etch rate of 75 ${\mu}m/min$ also lower side etch value after PSG etching. This method facilitates the microfabrication of PSG with various patterns and high aspect ratio for applying to advanced applications.

He-Cd 레이저와 근접장현미경을 이용한 폴리머박막 나노리소그라피 공정의 특성분석 (Characteristics of nanolithograpy process on polymer thin-film using near-field scanning optical microscope with a He-Cd laser)

  • 권상진;김필규;천채민;김동유;장원석;정성호
    • 한국레이저가공학회지
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    • 제7권3호
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    • pp.37-46
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    • 2004
  • The shape and size variations of the nanopatterns produced on a polymer film using a near-field scanning optical microscope(NSOM) are investigated with respect to the process variables. A cantilever type nanoprobe having a 100nm aperture at the apex of the pyramidal tip is used with the NSOM and a He-Cd laser at a wavelength of 442nm as the illumination source. Patterning characteristics are examined for different laser beam power at the entrance side of the aperture($P_{in}$), scan speed of the piezo stage(V), repeated scanning over the same pattern, and operation modes of the NSOM(DC and AC modes). The pattern size remained almost the same for equal linear energy density. Pattern size decreased for lower laser beam power and greater scan speed, leading to a minimum pattern width of around 50nm at $P_{in}=1.2{\mu}W\;and\;V=12{\mu}m/s$. Direct writing of an arbitrary pattern with a line width of about 150nm was demonstrated to verify the feasibility of this technique for nanomask fabrication. Application on high-density data storage is discussed.

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Electrical Characteristic of IGZO Oxide TFTs with 3 Layer Gate Insulator

  • Lim, Sang Chul;Koo, Jae Bon;Park, Chan Woo;Jung, Soon-Won;Na, Bock Soon;Lee, Sang Seok;Cho, Kyoung Ik;Chu, Hye Yong
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2014년도 제46회 동계 정기학술대회 초록집
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    • pp.344-344
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    • 2014
  • Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

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High Quality Nickel Atomic Layer Deposition for Nanoscale Contact Applications

  • Kim, Woo-Hee;Lee, Han-Bo-Ram;Heo, Kwang;Hong, Seung-Hun;Kim, Hyung-Jun
    • 한국재료학회:학술대회논문집
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    • 한국재료학회 2009년도 춘계학술발표대회
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    • pp.22.2-22.2
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    • 2009
  • Currently, metal silicides become increasingly more essential part as a contact material in complimentary metal-oxide-semiconductor (CMOS). Among various silicides, NiSi has several advantages such as low resistivity against narrow line width and low Si consumption. Generally, metal silicides are formed through physical vapor deposition (PVD) of metal film, followed by annealing. Nanoscale devices require formation of contact in the inside of deep contact holes, especially for memory device. However, PVD may suffer from poor conformality in deep contact holes. Therefore, Atomic layer deposition (ALD) can be a promising method since it can produce thin films with excellent conformality and atomic scale thickness controllability through the self-saturated surface reaction. In this study, Ni thin films were deposited by thermal ALD using bis(dimethylamino-2-methyl-2-butoxo)nickel [Ni(dmamb)2] as a precursor and NH3 gas as a reactant. The Ni ALD produced pure metallic Ni films with low resistivity of 25 $\mu{\Omega}cm$. In addition, it showed the excellent conformality in nanoscale contact holes as well as on Si nanowires. Meanwhile, the Ni ALD was applied to area-selective ALD using octadecyltrichlorosilane (OTS) self-assembled monolayer as a blocking layer. Due to the differences of the nucleation on OTS modified surfaces toward ALD reaction, ALD Ni films were selectively deposited on un-coated OTS region, producing 3 ${\mu}m$-width Ni line patterns without expensive patterning process.

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