• 한국응용과학기술학회지
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• 제34권3호
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• pp.643-649
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• 2017

리파아제 및 프로테이나아제와 같은 생분해성 효소는 지방산 에스테르 및 트리글리 세라이드뿐만 아니라 지방족 폴리에스테르를 가수 분해가 가능하다. 본 연구에서는 생분해성 효소가 자연 환경에서 PLA, 옥수수 전분 및 폴리에틸렌글리콜 등의 천연 지방족 폴리 물질이 분해에 중요한 역할인 생분해성을 측정했다. 본 실험에서는 PLA, PLA와 폴리에틸렌아크릴레이트, PLA 그라프트 중합체인 폴리에틸렌글리콜아크릴레이트를 사용한 PLAcoPolyethylene의 생분해성에 대해 실험하였다. 생분해성 고분자를 합성할 때. 이들의 기계적 특성은 생분해성도, 열적특성, 실시간으로 폴리머 수지의 전기적 모니터링을 통해 실험측정 결과, BOD와 PLAcoPolyethylene의 생분해도는 PLA와 그라프트 공중합된 폴리에틸렌아크릴레이트는 다른 시료보다 낮은 속도로 측정되었다.

• 전자공학회논문지D
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• 제35D권3호
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• pp.39-45
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• 1998

SrBi$_{2}$Ta$_{2}$O$_{9}$ (SBT) ferroelectric thin films for nonvolatile memory were prepared on Pt/Ti/SiO$_{2}$/Si and RuO$_{2}$/SiO$_{2}$/Si substrates by RF magnetron sputtering. The dependences of crystalline and electrical properties on the lower electrode type(Pt and RuO$_{2}$) and the annealing temperatures were investigated. SBT films regardless of their electrode types showed typeical Bi layered peroviskite crystal structures. The crystalline quality of as-deposited SBT films was improved by the rapid thermal annealing at 650.deg. C for 30 sec. The remanetn polarization of 2Pr (Pr+-Pr-) of the annealed SBT films deposited on Pt/Ti/SiO$_{2}$/Si substrates were about 11 .mu.C/cm$^{2}$ and 3 .mu.C/cm$^{2}$, respectively. The leakage currents at 3 V bias voltage were about 0.8 .mu.A/cm$^{2}$ for SBT/ Pt/Ti/SiO$_{2}$/Si and about 1 .mu.A/cm$^{2}$ for SBT/RuO$_{2}$/SiO$_{2}$/Si sample. SBT films annealed at 650 .deg. C showed no degradation in Pr values after 10$^{11}$ polarization switching cycles, indicating good fatigue properties. In addition, for SBT samples deposited on Pt/Ti/SiO$_{2}$/Si, Pr values increased to more than that of initial state, suggesting the increament of leakage current caused by repeated polarization.

• 한국표면공학회지
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• 제49권6호
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• pp.530-538
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• 2016

There is a close relationship between the performance and the heat generation of the electronic device. Heat generation causes a significant degradation of the durability and/or efficiency of the device. It is necessary to have an effective method to release the generated heat. Based on demands of the printed circuit board (PCB) manufacturing, it is necessary to develop a robust and reliable plating technique for substrates with high thermal conductivity, such as alumina ($Al_2O_3$), aluminium nitride (AlN), and silicon nitride ($Si_3N_4$). In this study, the plating of metal layers on an insulating silicon nitride ($Si_3N_4$) ceramic substrate was developed. We formed a Pd-$TiO_2$ adhesion layer and used APTES(3-Aminopropyltriethoxysilane) to form OH groups on the surface and adhere the metal layer on the insulating $Si_3N_4$ substrate. We used an electroless Ni plating without sensitization/activation process, as Pd particles were nucleated on the $TiO_2$ layer. The electrical resistivity of Ni and Cu layers is $7.27{\times}10^{-5}$ and $1.32{\times}10^{-6}ohm-cm$ by 4 point prober, respectively. The adhesion strength is 2.506 N by scratch test.

• 한국재료학회지
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• 제10권4호
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• pp.301-304
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• 2000

Si FEA로 부터 tip의 표면을 Co 금속으로 silicidation한 새로운 3극형 Co-silicided Si FEA를 제작하고 이의 전계 방출특성을 조사하였다. $10^{-8}Torr$의 고진공상태에서 제작된 소자의 단위 pixel(pixel 면적 : $250{\mu\textrm{m}}{\times}250{\mu\textrm{m}}$, tip 어레이 : $45{\times}45$)를 통해 측정된 turn-on 전압은 약 35V로, 아노드 전류는 $V_A=500V,\;V_G=55V$ 바이어스 아래에서 약 $1.2{\mu\textrm{A}}(0.6nA/tip)$로 나타났다. 제작된 소자는 초기 과도상태를 제외하면 장시간의 동작을 통해 전계방출 전류의 감소없이 매우 안정된 전기적 특성을 나타내었다. Co-silicided Si FFA 의 낮은 turn-on 전압과 높은 전류안전성은 Si tip 표면에 형성된 실리사이드 박막의 열화학적 안전성과 낮은 일함수에 기인하는 것으로 판단된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 추계학술대회 논문집
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• pp.5-5
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• 2009

Thin-film-transistors (TFTs) that can be prepared at low temperatures have attracted much attention because of the great potential for transparent and flexible electronics. One of the mainstreams in this field is the use of organic semiconductors such as pentacene. But device performance of the organic TFTs is still limited due to low field-effect mobility and rapid degradation after exposing to air. Alternative approach is the use of amorphous oxide semiconductors as a channel. Amorphous oxide semiconductors (AOSs) based TFTs showed the fast technological development, because AOS films can be fabricated at room temperature and exhibit the possibility in application like flexible display, electronic paper, and larges solar cells. Among the various AOSs, a-IGZO has lots of advantages because it has high channel mobility, uniform surface roughness and good transparency. [1] The high mobility is attributed to the overlap of spherical s-orbital of the heavy post-transition metal cations. This study demonstrated the effect of the variation in channel thickness from 30nm to 200nm on the TFT device performance. When the thickness was increased, turn-on voltage and subthreshold swing was decreased. The a-IGZO channels and source/drain metals were deposited with shadow mask. The a-IGZO channel layer was deposited on $SiO_2$/p-Si substrates by RF magnetron sputtering, where RF power is 150W. And working pressure is 3m Torr, at $O_2/Ar$ (2/28 sccm) atmosphere. The electrodes were formed with electron-beam evaporated Ti (30 nm) and Au (70 nm) bilayer. Finally, Al (150nm) as a gate metal was thermal-evaporated. TFT devices were heat-treated in a furnace at 250 $^{\circ}C$ and nitrogen atmosphere for 1hour. The electrical properties of the TFTs were measured using a probe-station. The TFT with channel thickness of 150nm exhibits a good subthreshold swing (SS) of 0.72 V/decade and on-off ratio of $1{\times}10^8$. The field effect mobility and threshold voltage were evaluated as 7.2 and 8 V, respectively.

• 한국재료학회지
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• 제19권1호
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• pp.28-32
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• 2009

Silicon carbide (SiC) is a promising material for power device applications due to its wide band gap (3.26 eV for 4H-SiC), high critical electric field and excellent thermal conductivity. The Schottky barrier diode is the representative high-power device that is currently available commercially. A field plate edge-terminated 4H-SiC was fabricated using a lift-off process for opening the Schottky contacts. In this case, Ni/Ti dual-metal contacts were unintentionally formed at the edge of the Schottky contacts and resulted in the degradation of the electrical properties of the diodes. The breakdown voltage and Schottky barrier height (SBH, ${\Phi}_B$) was 107 V and 0.67 eV, respectively. To form homogeneous single-metal Ni/4H-SiC Schottky contacts, a deposition and etching method was employed, and the electrical properties of the diodes were improved. The modified SBDs showed enhanced electrical properties, as witnessed by a breakdown voltage of 635 V, a Schottky barrier height of ${\Phi}_B$=1.48 eV, an ideality factor of n=1.04 (close to one), a forward voltage drop of $V_F$=1.6 V, a specific on resistance of $R_{on}=2.1m{\Omega}-cm^2$ and a power loss of $P_L=79.6Wcm^{-2}$.

• Current Photovoltaic Research
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• 제2권4호
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• pp.168-172
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• 2014

Under concentrated illuminations, the solar cells show higher efficiencies mainly due to an increase of the open circuit voltage. In this study, InGaP/InGaAs/Ge triple-junction solar cells have been grown by a low pressure metalorganic chemical vapor deposition. Photovoltaic characteristics of the fabricated solar cells are investigated with a class A solar simulator under concentrated illuminations from 1 to 100 suns. Ideally, the open circuit voltage should increase with the current level when maintained at the same temperature. However, the fabricated solar cells show degraded open circuit voltages under high concentrations around 100 suns. This means that the heat sink design is not optimized to keep the cell temperature at $25^{\circ}C$. To demonstrate the thermal degradation, changes of the device performance are investigated with different bonding conditions and heat sink materials.

• 공업화학
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• 제19권2호
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• pp.161-167
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• 2008

다층카본나노튜브(MWCNT)가 강화된 폴리에틸렌에틸아크릴레이트(EEA) 나노복합체를 용융혼합법과 용액혼합법으로 제조하였다. 카본나노튜브의 형태 및 함량변화에 따른 기계적, 열적, 전기적 특성을 조사하였다. MWCNT의 함량이 증가함에 따라 인장강도, 모듈러스는 증가하였고, 파단신장률은 감소하였다. 할로우 형태의 MWCNT가 일반적인 MWCNT에 비해 우수한 인장강도 및 파단신장률을 나타내었다. MWCNT 함량이 증가함에 따라 약 $40^{\circ}C$의 열분해온도의 향상을 보였다. 전기적 특성은 용융혼합법의 경우가 가장 높은 전기저항 특성을 나타내었고, 용액혼합법의 경우 일반형 MWCNT가 할로우 MWCNT보다 낮은 체적저항을 보였다. MWCNT의 함량이 증가할수록 파단면 위로 돌출되는 CNT 수가 증가하였고, 인장변형을 가하면 표면 위로 돌출되는 CNT 수와 길이가 크게 증가하였다. 용융혼합된 시편이 용액혼합에 비해 돌출된 CNT의 수와 길이가 현격히 낮았다.

• 한국표면공학회:학술대회논문집
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• 한국표면공학회 2018년도 춘계학술대회 논문집
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.

• 폴리머
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• 제36권2호
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• pp.155-162
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• 2012

전기방사 방법으로 sulfonated poly(ether ether ketone) (SPEEK) 나노섬유를 제조하고, 압축성형법으로 고분자 전해질막 연료전지(polymer electrolyte membrane fuel cell, PEMFC)용 나노섬유막을 제조하였다. SPEEK의 최대 설폰화율은 95% 이었고 초기 열분해 온도는 약 $280^{\circ}C$로 PEEK 보다 낮았으며 접촉각은 설폰화도가 증가함에 따라 감소하였다. 전기방사 나노섬유의 최적 인가전압, 유속, 방사거리(tip to collector distance, TCD) 및 농도는 각각 22 kV, 0.3 mL/hr, 5 cm, 23 wt% 이었고 평균 섬유직경은 47.6 nm 이었다. 한편, SPEEK 이온교환 나노섬유막의 함수율 및 이온교환용량은 설폰화 시간과 설폰화제 함량이 증가함에 따라 증가하였으며 최적값은 각각 20%, 2.03 meq/g으로 Nafion 117 보다 우수하였다. 막의 전기저항은 설폰화 시간이 증가함에 따라 감소하였고 그 값은 0.58~0.06 ${\Omega}{\cdot}cm^2$로 측정되었다. 또한 막의 수소이온전도도는 설폰화 시간이 증가함에 따라 증가하였으며 최대 0.099 S/cm로 Nafion 117 보다 우수하였다.