• Journal of the Korean Institute of Telematics and Electronics B
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• v.31B no.9
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• pp.1-9
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• 1994

This paper analyzes the faults and their mechanism of CMOS ICs using IDDQ testing technique and evalutes the reliability of the chips that fail this test. It is implemented by the three testing phases, initial test, burn-in and life test. Each testing phase includes the parametric test, functional test, IDDQ test and propagation delay test. It is shown that the short faults such as gate-oxide short, bridging can be only detected by IDDQ testing technique and the number of test patterns for this test technique is very few. After first burn-in, the IDDQ of some test chips is decreased, which is increased in conventional studies and in subsequent burn-in, the IDDQ of all test chips is stabilized. It is verified that the resistive short faults exist in the test chips and it is deteriorated with time and causes the logic fault. Also, the new testing technique which can easily detect the rsistive short fault is proposed.

• Journal of Information Processing Systems
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• v.7 no.2
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• pp.363-384
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• 2011

As the complexity of software is increasing, generating an effective test data has become a necessity. This necessity has increased the demand for techniques that can generate test data effectively. This paper proposes a test data generation technique based on adequacy based testing criteria. Adequacy based testing criteria uses the concept of mutation analysis to check the adequacy of test data. In general, mutation analysis is applied after the test data is generated. But, in this work, we propose a technique that applies mutation analysis at the time of test data generation only, rather than applying it after the test data has been generated. This saves significant amount of time (required to generate adequate test cases) as compared to the latter case as the total time in the latter case is the sum of the time to generate test data and the time to apply mutation analysis to the generated test data. We also use genetic algorithms that explore the complete domain of the program to provide near-global optimum solution. In this paper, we first define and explain the proposed technique. Then we validate the proposed technique using ten real time programs. The proposed technique is compared with path testing technique (that use reliability based testing criteria) for these ten programs. The results show that the adequacy based proposed technique is better than the reliability based path testing technique and there is a significant reduce in number of generated test cases and time taken to generate test cases.

• Journal of KIISE
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• v.42 no.11
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• pp.1386-1396
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• 2015

Graphical user interface testing (GUI testing) techniques have been widely used to test the functionality of Android applications (apps) and to detect faults for verification of the reliability and usability of apps. To adequately test the behaviors of apps, a number of studies on model-based GUI testing techniques have been performed on Android apps. However, the effectiveness of model-based techniques greatly depends on the quality of the GUI model, because model-based GUI testing techniques generate test inputs based on this model. Therefore, in order to improve testing effectiveness in model-based techniques, accurate and efficient GUI model generation has to be achieved using an improved model generation technique with concrete definition of GUI states. For accurate and efficient generation of a GUI model and test inputs, this study suggests a hierarchical GUI state comparison technique and evaluates this technique through comparison with the existing model-based techniques, considering activities as GUI states. Our results show that the proposed technique outperforms existing approaches and has the potential to improve the performance of model-based GUI testing techniques for Android apps.

• Journal of the Korean Institute of Gas
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• v.16 no.1
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• pp.22-25
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• 2012

Welding and/or fusion in polyethylene(PE) system made on site is focused on the control of the welding or fusion process to follow proper procedure. The process control is important, but it is not sufficient for the long term reliability of a pipe system. To achieve the rate of failure close to zero, Non Destructive Testing(NDT) is necessary in addition to joining process control. For electrofusion joints several non-destructive testing methods are available. The ultrasonic phased array technique is possible to detect various defects including wire deviations and regions with lack of fusion. In this studies, testing was carried to detect the defect after electrofusion joining of polyethylene piping is utilized by the ultrasonic phased array technique. From testing data, ultrasonic phased array technique is recommended as a reliable non-destructive testing method.

• Journal of Information Processing Systems
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• v.6 no.1
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• pp.21-32
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• 2010

Software maintenance is one of the major activities of the software development life cycle. Due to the time and cost constraint it is not possible to perform exhaustive regression testing. Thus, there is a need for a technique that selects and prioritizes the effective and important test cases so that the testing effort is reduced. In an analogous study we have proposed a new variable based algorithm that works on variables using the hybrid technique. However, in the real world the programs consist of multiple modules. Hence, in this work we propose a regression testing algorithm that works on interprocedural programs. In order to validate and analyze this technique we have used various programs. The result shows that the performance and accuracy of this technique is very high.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.229-240
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• 1995

This paper proposes a new weighted random pattern testing technique to detect path delay faults in combinational logic circuits. When computing the probability of signal transition at primitive logic elements of CUT(Circuit Under Test) by the primary input, the proposed technique uses the information on the structure of CUT for initialization vectors and vectors generated by pseudo random pattern generator for test vectors. We can sensitize many paths by allocating a weight value on signal lines considering the difference of the levels of logic elements. We show that the proposed technique outperforms existing testing method in terms of test length and fault coverage using ISCAS '85 benchmark circuits. We also show that the proposed testing technique generates more robust test vectors for the longest and near-longest paths.

• Journal of the Korean Society for Nondestructive Testing
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• v.28 no.1
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• pp.64-69
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• 2008

In order to detect the internal defects which occur in welding parts of pressure vessel and structures, radiographic testing and ultrasonic testing is applied. However, because of the risks of radiation exposure and film processing, radiographic testing takes a relatively long time to verify the test results and it has affected in the production process. Typically, the manual ultrasonic testing is not easy to reproduce the result and it is highly dependent on the tester's skills. The TOFD technique, one of the automatic ultrasonic testings is spreading alternatively. This research describes the comparing test results by applying radiographic testing and TOFD technique to a mock-up specimen incruding the flaws. The TOFD technique will contribute to improve the objective reliability of the ultrasonic technique.

• Journal of Information Processing Systems
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• v.6 no.2
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• pp.235-252
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• 2010

Regression testing is a very costly process performed primarily as a software maintenance activity. It is the process of retesting the modified parts of the software and ensuring that no new errors have been introduced into previously tested source code due to these modifications. A regression test selection technique selects an appropriate number of test cases from a test suite that might expose a fault in the modified program. In this paper, we propose both a regression test selection and prioritization technique. We implemented our regression test selection technique and demonstrated in two case studies that our technique is effective regarding selecting and prioritizing test cases. The results show that our technique may significantly reduce the number of test cases and thus the cost and resources for performing regression testing on modified software.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.5 s.347
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• pp.34-47
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• 2006

In this paper, a new testing technique for core components of wireless transceiver was proposed. That was, band fault models (including the information of specifications in the analogue and RF IC) and methods which can test specifications in the time domain easily by observing a variation of band fault models in the circuit output were proposed and developed. This technique had an advantage over testing technique in frequency domain because it didn't need expensive test equipments and could reduce the time required. Test technique proposed in this paper was adapted to the test of 5.25 GHz low noise amplifier and proved that this testing technique was efficient in RF IC including low noise amplifier.

• 제어로봇시스템학회:학술대회논문집
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• 2005.06a
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• pp.792-793
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• 2005

Circuit testing process is very important in IC Manufacturing there are two ways in research for circuit testing improvement. These are ATPG Tool Design and Test simulation application. We are interested in how to use parallel technique such as one-side communication, parallel IO and dynamic Process with data partition for circuit testing improvement and we use one-side communication technique in this paper. The parallel ATPG Tool can reduce the test pattern sets of the circuit that is designed in laboratory for make sure that the fault is not occur. After that, we use result for parallel circuit test simulation to find fault between designed circuit and tested circuit. From the experiment, We use less execution time than non-parallel Process. And we can set more parameter for less test size. Previous experiment we can't do it because some parameter will affect much waste time. But in the research, if we use the best ATPG Tool can optimize to least test sets and parallel circuit testing application will not work. Because there are too little test set for circuit testing application. In this paper we use a standard sequential circuit of ISCAS89.