• The Journal of Korean Institute of Communications and Information Sciences
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• v.39B no.1
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• pp.1-7
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• 2014

This paper proposes an efficient test wrapper design that reduces overall test time in multi-core SoC. After initial local wrapper solution sets for all the cores are determined using well-known Combine algorithm, proposed algorithm selects a dominant core which consumes the longest test time in multi-core SoC. Then, the wrapper characteristics in the number of TAM wires and the test time for other cores are adjusted based on test time of the dominant core. For some specific cores, the number of TAM wires can be reduced by increasing its test time for design space exploration purposes. These modified wrapper characteristics are added to the previous wrapper solution set. By expanding previous local wrapper solution set to global wrapper solution set, overall test time for Multi-core SoC can be reduced by an efficient test scheduler. Effectiveness of the proposed wrapper is verified on ITC'02 benchmark circuits using $B^*$-tree based test scheduler. Our experimental results show that the test time is reduced by an average of 4.7% when compared to that of employing previous wrappers.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.3_4
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• pp.160-169
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• 2004

With an emergence of SOC from developed IC technology, the VLSI design has required the core re-use technique and modular test development. To minimize the cost of testing SOC, an efficient method is required to optimize the test time and area overhead in conjunction for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient design strategy of core test wrapper to achieve the minimum cost for SOC testing. The proposed strategy adopted advantages of traditional methods and more developed to be successfully used in practice.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.10 no.6
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• pp.1191-1195
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• 2009

We present the efficient test wrapper design methodology considering the layout distance of scan chain. To test the scan chains in SoC, the scan chains must be assigned to external TAM(Test Access Mechanism) lines. The scan chains in IP were placed and routed without any timing violation at normal mode. However, in test mode, the scan chains have the additional layout distance after TAM line assignment, which can cause the timing violation of flip-flops in scan chains. This paper proposes a new test wrapper design considering layout distance of scan chains with timing violation free.

• Proceedings of the KAIS Fall Conference
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• 2008.05a
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• pp.189-191
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• 2008

본 논문에서는 스캔 체인의 레이아웃 거리를 고려한 효율적인 Test Wrapper 설계 방식을 제안한다. SoC내의 스캔체인들을 테스트 하기 위해서는 외부 TAM line에 각 스캔체인들을 할당해야 한다. IP 내에 존재하는 스캔체인들은 스캔체인간 레이아웃 거리를 갖게 되며 이 거리가 클럭주기를 넘어가는 경우 체인의 타이밍 위반(Timing violation)이 발생될 수 있다. 본 논문에서는 타이밍 위반이 발생하지 않도록 체인간 거리를 고려하여 스캔체인을 할당하는 새로운 test wrapper 설계 방식을 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.3
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• pp.65-70
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• 2004

The SOC(System on Chip) testing has required the core re-use methodology and the efficiency of test method because of increase of its cost. The goal of SOC testing is to minimize the testing time, area overhead, and power consumption during testing. Prior research has concentrated on only one aspect of the test core wrapper design problem at a test time. Our research is concentrated on optimization of test time and area overhead for the core test wrapper, which is one of the important elements for SOC test architecture. In this paper, we propose an efficient wrapper design algorithm that improves on earlier approaches by also reducing the TAM(Test Access Mechanism) width required to achieve these lower testing times.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.61-68
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• 2008

This paper introduces an embedded core test wrapper for AMBA based System-on-Chip(SoC) test. The proposed test wrapper is compatible with IEEE 1500 and can be controlled by ARM Test Interface Controller(TIC). We use IEEE 1500 wrapper boundary registers as temporal registers to load test results as well as test patterns and apply a modified scan test procedure. Test time is reduced by simultaneously performing primary input insertion and primary output observation as well as scan-in and scan-out.

• Journal of Biosystems Engineering
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• v.27 no.3
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• pp.195-202
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• 2002

In order to make a winter cereal wrap silage, a tractor attached round bale wrapper was developed locally. Its specific structure and various functions were reported in the last submitted paper. In this study a control system of bale wrapper combining with the actuators of various processes was developed to make round bale wrapper compatible in the field. Also. its performance was tested by making the rye round bale. The results can be summarized as fellow. 1. The field capacity of round bale wrapping was investigated around 0.5 ha/hr, and the operating time of bale wrapper was about 3 min for each 500kg round bale 2. Plastic film which has maximum elongation rate of 796% was stretched to 150∼170% of original length and was lessened to 80∼90% of original width. 3. In the quality test of bale produced by developed bale wrapper, there was no significant changes of moisture contents if it was wrapped more than 4 layers of 25 ㎛-plastic film. 4. Also. temperature of the wrapped bale was about 33$\^{C}$ in the beginning of fermentation and was stabled to 26∼29$\^{C}$ during one month or more storage. Therefore, wrapping performance of the developed bale wrapper was properly.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.2
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• pp.226-235
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• 2016

The yield of 3D stacked IC manufacturing improves with the pre-bond integrity testing of through silicon vias (TSVs). In this paper, an efficient pre-bond test method is presented based on IEEE std. 1500, which can precisely diagnose any happening of TSV defects. The IEEE std. 1500 wrapper cells are augmented for the proposed method. The pre-bond TSV test can be performed by adjusting the driving strength of TSV drivers and the test clock frequency. The experimental results show the advantages of the proposed approach.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.704-716
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• 2005

Assembling new software systems from Prepared components is an attractive alternative to traditional software development method to reduce development cost and schedule dramatically. However, if separately developed components are tested, integrated and verified with unreasonable effort and high cost, it would not be an effective way to software development. Components are not distributed in the shape of white-box source code so that should be hard to validate and test in new application environment. For solving this problem, built-in tester components are suggested to check the contract-compliance of their server components. If components have various and complex function, built-in tester should be heavy and unflexible to test in composition of components. This paper suggests enhancing automated wrapper technique which substitutes with built-in tester components and shows the usability of the wrapper by design and implementation. Component testing in this way reduces the cost and effort associated with preparation of component testing and makes the various test experiments in components assembly.