• 정보처리학회논문지D
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• 제16D권3호
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• pp.371-380
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• 2009

최근에 테스트 데이터를 자동으로 생성하는 방법에 관한 연구가 활발하게 진행되고 있다. 그러나 이러한 방법들은 플래그 변수가 프로그램에 존재하는 경우에는 효과적이지 못함이 밝혀졌다. 이는 엔진 제어기와 같은 내장형 시스템들이 전형적으로 디바이스 관련 상태 정보를 기록하기 위해 플래그 변수를 많이 이용한다는 점을 고려할 때 문제가 된다. 이 논문에서는 플래그 변수가 있는 프로그램에 대하여 효과적으로 테스트 데이터를 생성할 수 있는 방법을 소개한다. 이 방법은 테스트 데이터 생성 문제를 SAT(SATisfiability) 문제로 변환하고 SAT 해결도구를 이용하여 자동으로 테스트 데이터를 생성한다. 이를 위해 프로그램을 1차 관계 논리 언어인 Alloy로 변환하고 Alloy 분석기를 통하여 테스트 데이터를 생성한다.

• 대한전자공학회논문지
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• 제27권7호
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• pp.1118-1127
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• 1990

In this paper a new test generation method for Domino CMOS logic circuits is proposed. Because the stuck-at type fault is not adequate for Domino CMOS circuits the stuck-open fault, stuck-on fault and bridging fault are considered as fault models. It is shown that the test generation problem of Domino CMOS circuits results in functional block test generation problem. Test set is generated by using the logic minimizer which is a part of logic design system. An algorithm for reduction of test set is described. The proposed test method can be easily applied to various figures of circuits and make it easy to construct automatic test generator in design system. The proposed algorithms are programed and their efficiency is confirmed by examples.

• Management Science and Financial Engineering
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• 제11권2호
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• pp.85-103
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• 2005

In this paper, we consider the routing and wavelength assignment problem in survivable WDM transport network without wavelength conversion. We assume the single-link failure and a path protection scheme in optical layer. When a physical network and a set of working paths are given, the problem is to select a link-disjoint protection path for each working path and assign a wavelength for each working and protection path. We give an integer programming formulation of the problem and propose an algorithm to solve it. Though the formulation has exponentially many variables, we solve the linear programming relaxation of it by using column generation technique. We devise a branch-and price algorithm to solve the column generation problem. After solving the linear programming relaxation, we apply a variable fixing procedure combined with the column generation to get an integral solution. We test the proposed algorithm on some randomly generated data and test results show that the algorithm gives very good solutions.

• 공학교육연구
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• 제2권1호
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• pp.17-23
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• 1999

인터넷을 이용한 여러 가지의 서비스 중에서도 학습 관리를 인터넷에서 처리할 수 있도록 하는 시스템이 속속 개발되고 있다. 본 논문에서는 현재 상용화 된 인터넷용 문제 출제 및 평가시스템의 성능을 비교 분석하고 이를 학습에 적용하기 위한 구체적인 방법들을 제시한 후 국내의 독자적인 기술력으로 저자가 개발한 JPGEM(Java Problem Generation and Evaluation Module) 에 대하여 간략히 설명하고자 한다. JPGEM 은 종합 문제 출제 및 평가 시스템으로 자바를 이용하여 개발되었으며, 개별 교과목에 관한 문제를 임의로 출제할 수 있다. 총 5가지의 문제 출제 유형을 지원하고 시험 결과를 서버에 저장하여 학습자의 학습 및 능력을 평가할 수 있도록 지원한다.

• 인터넷정보학회논문지
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• 제9권2호
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• pp.89-105
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• 2008

지금까지 테스트 데이터를 자동으로 생성하기 위한 대부분의 연구는 프로그램에 포인터가 존재하지 않는 경우만을 대상으로 하였다. 최근에 포인터가 있는 경우에도 테스트 데이터를 자동으로 생성할 수 있는 방법들이 제안되었지만 테스트할 프로그램 경로를 완전하게 명시해야 하는 경로 기반 방법이거나 프로그램을 실제 실행해야 하는 방법들이다. 이 논문에서는 프로그램 경로를 완전하게 명시하지 않아도 포인터가 있는 프로그램에 대하여 테스트 데이터를 생성할 수 있는 새로운 방법을 제안한다. 제안된 방법은 테스트 데이터 생성 문제를SAT(SATisfiability) 문제로 변환하고 SAT 해결도구를 이용하여 자동으로 테스트 데이터를 생성하는 정적 방법이다. 이를 위해 프로그램을 1차 관계 논리 언어인 Alloy로 변환하고 Alloy 분석기를 통하여 테스트 데이터를 생성한다.

• ETRI Journal
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• 제23권3호
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• pp.138-149
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• 2001

Due to the rapidly growing complexity of VLSI circuits, test methodologies based on delay testing become popular. However, most approaches cannot handle custom logic blocks which are described by logic functions rather than by circuit primitive elements. To overcome this problem, a new path delay test generation algorithm is developed for custom designs. The results using benchmark circuits and real designs prove the efficiency of the new algorithm. The new test generation algorithm can be applied to designs employing intellectual property (IP) circuits whose implementation details are either unknown or unavailable.

• 한국경영과학회지
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• 제25권3호
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• pp.17-33
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• 2000

We consider the Steiner tree packing problem. For a given undirected graph G =(V, E) with positive integer capacities and non-negative weights on its edges, and a list of node sets(nets), the problem is to find a connection of nets which satisfies the edge capacity limits and minimizes the total weights. We focus on the switchbox routing problem in knock-knee model and formulate this problem as an integer programming using Steiner tree variables. The model contains exponential number of variables, but the problem can be solved using a polynomial time column generation procedure. We test the algorithm on some standard test instances and compare the performances with the results using cutting plane approach. Computational results show that our algorithm is competitive to the cutting plane algorithm presented by Grotschel et al. and can be used to solve practically sized problems.

• Journal of Advanced Marine Engineering and Technology
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• 제22권5호
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• pp.687-692
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• 1998

Test pattern generation is one of most difficult problems encountered in automating the design of logic circuits. The goal is to obtain the highest fault coverage with the minimum number of test patterns for a given circuit and fault set. although there have been many deterministic algorithms and heuristics the problem is still highly complex and time-consuming. Therefore new approach-es are needed to augment the existing techniques. This paper considers the problem of test pattern improvement for combinational circuits as a restricted subproblem of the test pattern generation. The problem is to maximize the fault coverage with a fixed number of test patterns for a given cir-cuit and fault set. We propose a new approach by use of a genetic algorithm. In this approach the genetic algorithm evolves test patterns to improve their fault coverage. A fault simulation is used to compute the fault coverage of the test patterns Experimental results show that the genetic algorithm based approach can achieve higher fault coverages than traditional techniques for most combinational circuits. Another advantage of the approach is that the genetic algorithm needs no detailed knowledge of faulty circuits under test.

• 한국경영과학회:학술대회논문집
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• 한국경영과학회 2001년도 추계학술대회 논문집
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• pp.124-127
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• 2001

We consider the routing and wavelength assignment problem in survivable WDM transport network without wavelength conversion. We assume the single-link failure and a path protection scheme in optical layer. When a physical network and a set of working paths are given, the problem is to select a link-disjoint protection path for each working path and assign a wavelength for each working and protection path. We give an integer programming formulation of the problem and propose an algorithm to solve it based on column generation technique and variable fixing. We devise a branch-and-price algorithm to solve the column generation problem. We test the proposed algorithm on some randomly generated data and test results show that the algorithm gives very good solutions.

• 전자공학회논문지A
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• 제30A권2호
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• pp.63-75
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• 1993

As the CMOS technology becomes the most dominant circuit realization method, the cost problem for the test which includes both the transistor-level FET stuck-on and stuck-off faults and the gatelevel stuck-at faults becomes more and more serious. In accordance, this paper proposes a test set and its generation algorithm, which handles both the transistor-level faults and the gate-level faults, thus can unify the test steps during the IC design and fabrication procedure. This algorithm uses only the logic equation of the given logic function as the input resource without referring the transistor of gate circuit. Also, the resultant test set from this algorithm can improve in both the complexity of the generation algorithm and the time to apply the test as well as unify the test steps in comparing the existing methods.