• ETRI Journal
• /
• v.36 no.4
• /
• pp.635-642
• /
• 2014

Three-dimensional integrated circuits (3D ICs) implement heterogeneous systems in the same platform by stacking several planar chips vertically with through-silicon via (TSV) technology. 3D ICs have some advantages, including shorter interconnect lengths, higher integration density, and improved performance. Thermal-aware design would enhance the reliability and performance of the interconnects and devices. In this paper, we propose thermal-aware floorplanning with min-cut die partitioning for 3D ICs. The proposed min-cut die partition methodology minimizes the number of connections between partitions based on the min-cut theorem and minimizes the number of TSVs by considering a complementary set from the set of connections between two partitions when assigning the partitions to dies. Also, thermal-aware floorplanning methodology ensures a more even power distribution in the dies and reduces the peak temperature of the chip. The simulation results show that the proposed methodologies reduced the number of TSVs and the peak temperature effectively while also reducing the run-time.

• ETRI Journal
• /
• v.37 no.1
• /
• pp.118-127
• /
• 2015

The power consumption of 3D many-core processors can be reduced, and the power delivery of such processors can be improved by introducing voltage island (VI) design using on-chip voltage regulators. With the dramatic growth in the number of cores that are integrated in a processor, however, it is infeasible to adopt per-core VI design. We propose a 3D many-core processor architecture that consists of multiple voltage clusters, where each has a set of cores that share an on-chip voltage regulator. Based on the architecture, the steady state temperature is analyzed so that the thermal characteristic of each voltage cluster is known. In the voltage scaling and task scheduling stages, the thermal characteristics and communication between cores is considered. The consideration of the thermal characteristics enables the proposed VI formation to reduce the total energy consumption, peak temperature, and temperature gradients in 3D many-core processors.

• Journal of the Institute of Convergence Signal Processing
• /
• v.23 no.2
• /
• pp.50-61
• /
• 2022

This work demonstrates the design and evaluation of Aqua-Aware, a lightweight miniaturized light emitting diode (LED) based underwater compact sensor node which is used to obtain different characteristics of the underwater environment. Two optical sensor nodes have been designed, developed, and evaluated for a short and medium link range called as Aqua-Aware short range (AASR) and Aqua-Aware medium range (AAMR), respectively. The hardware and software implementation of proposed sensor node, algorithms, and trade-offs have been discussed in this paper. The underwater environment is emulated by introducing different turbulence effects such as air bubbles, waves and turbidity in a 4-m water tank. In clear water, the Aqua-Aware achieved a data rate of 0.2 Mbps at communication link up to 2-m. The Aqua-Aware was able to achieve 0.2 Mbps in a turbid water of 64 NTU in the presence of moderate water waves and air bubbles within the communication link range of 1.7-m. We have evaluated the luminous intensity, packet success rate and bit error rate performance of the proposed system obtained by varying the various medium characteristics.

• Journal of Advanced Navigation Technology
• /
• v.14 no.3
• /
• pp.432-438
• /
• 2010

In this paper, we propose a system which can perceive status of semiconductor equipment and evaluate its performance. The proposed system acquires the information such acceleration, pressure, temperature and gas sensors in the surrounding semiconductor equipment. After acquiring information, it is sent to server through multi hop transmission. The transmitted data generates 3 steps alarm using context-aware algorithm of unit or multiple event. From the experiment's result of the proposed system, we confirm that the reliability and efficiency of information is more improved about 80% than a system that doesn't use context-aware algorithm. Moreover, this system can be effective status monitoring of semiconductor equipment because lots of client nodes acquire surrounding information.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.13 no.2
• /
• pp.87-97
• /
• 2013

Negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI) are critical circuit reliability issues in highly scaled CMOS technologies. In this paper, we analyze the impacts of NBTI and PBTI on SRAM $V_{MIN}$, and present a design solution for mitigating the impact of NBTI and PBTI on SRAM $V_{MIN}$. Two different types of SRAM $V_{MIN}$ (SNM-limited $V_{MIN}$ and time-limited $V_{MIN}$) are explained. Simulation results show that SNM-limited $V_{MIN}$ is more sensitive to NBTI while time-limited $V_{MIN}$ is more prone to suffer from PBTI effect. The proposed NBTI/PBTI-aware control of wordline pulse width and woldline voltage improves cell stability, and mitigates the $V_{MIN}$ degradation induced by NBTI/PBTI.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2010.05a
• /
• pp.547-549
• /
• 2010

In this paper, we propose context-aware system for semiconductor equipment that acquires information from multiple sensors in indoor environment. This proposed system acquires information from acceleration, pressure, temperature and gas sensors then the acquired information send to server. The data transmitted to server generates an alarm via context-aware algorithm of unit event and multi event. From that result, high-quality real-time monitoring is possible because of the reduced unnecessary alarms, and the efficient management is possible because the surrounding information is recognized at once.

• Journal of KIISE:Computer Systems and Theory
• /
• v.36 no.6
• /
• pp.532-542
• /
• 2009

Dynamic Thermal Management (DTM) technique is generally used for reducing the peak temperature (hotspot) in the microprocessors. Despite the advantages of lower cooling cost and improved stability, the DTM technique inevitably suffers from performance loss. This paper proposes the DualFloating-Point Adders Architecture to minimize the performance loss due to thermal problem when the floating-point applications are executed. During running floating-point applications, only one of two floating-point adders is used selectively in the proposed architecture, leading to reduced peak temperature in the processor. We also propose a new floorplan technique, which creates Space for Heat Transfer Delay in the processor for solving the thermal problem due to heat transfer between adjacent hot units. As a result, the peak temperature drops by $5.3^{\circ}C$ on the average (maximum $10.8^{\circ}C$ for the processor where the DTM is adopted, consequently giving a solution to the thermal problem. Moreover, the processor performance is improved by 41% on the average by reducing the stall time due to the DTM.

• Journal of the Korea Society of Computer and Information
• /
• v.15 no.11
• /
• pp.1-9
• /
• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
• /
• v.22 no.2
• /
• pp.1-9
• /
• 2008

Light is a critical element for people to live and do creative activities in residential buildings. Especially, light in the dim)ing room is the most important factor for psychological and emotional effects but people are living under the poor light environment. Most people even are not well aware of good lighting environment. Also, the domestic lighting designers just follow the Korean Standards illuminance but it isn't appropriated for our cultural and social sides. This study investigated illuminance and color temperature of dining tables, and also analyzed the results of those in actual residential buildings.

• Journal of Computing Science and Engineering
• /
• v.4 no.3
• /
• pp.189-206
• /
• 2010

It is generally accepted that dynamic voltage scaling (DVS) is one of the most effective techniques of energy minimization for real-time applications in embedded system design. The effectiveness comes from the fact that the amount of energy consumption is quadractically proportional to the voltage applied to the processor. The penalty is the execution delay, which is linearly and inversely proportional to the voltage. According to the granularity of tasks to which voltage scaling is applied, the DVS problem is divided into two subproblems: inter-task DVS problem, in which the determination of the voltage is carried out on a task-by-task basis and the voltage assigned to the task is unchanged during the whole execution of the task, and intra-task DVS problem, in which the operating voltage of a task is dynamically adjusted according to the execution behavior to reflect the changes of the required number of cycles to finish the task before the deadline. Frequent voltage transitions may cause an adverse effect on energy minimization due to the increase of the overhead of transition time and energy. In addition, DVS needs to be carefully applied so that the dynamically varying chip temperature should not exceed a certain threshold because a drastic increase of chip temperature is highly likely to cause system function failure. This paper reviews representative works on the theoretical solutions to DVS problems regarding inter-task DVS, intra-task DVS, voltage transition, and thermal-aware DVS.