• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2003년도 하계학술대회 논문집 Vol.4 No.1
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• pp.96-99
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• 2003

In this paper, ageing diagnostics in the large capacity oil transformer are investigated. Following items are investigated for the ageing diagnostic in transformer oils (leakage current of sensor, power consumption and temperature of transformer oil). All temperature data are gathered from daily report in the substation. The power consumption of transformer are gathered output report of APIS(Airport Power Information System). Especially, data of sensor leakage current are accumulated from the online diagnostic system for transformer oil. The temperature of transformer oils major change factor was ambient temperature and capacity of power load. The leakage current are change by oil temperature. The leakage current ware not more than 2 [nA] in summer,

• 반도체디스플레이기술학회지
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• 제14권3호
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• pp.27-31
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• 2015

It was the electrical properties of ZnS treated by the annealing in a vaccum and an atmosphere conditions to reseached the leakage current effect of semiconductor devices. Most samples were shown the non-linear with unipolar properties, but the ZnS annealed at $100^{\circ}C$ in a vaccum was only observed no leakage current in a range of -20 V< voltage < 15 V. The crystallinity of ZnS with no leakage current was improved and optical property was also improved. Because the ambipolar characteristics and low leakage currents originated from the extension effect of a depletion width by electron-hole combination in the depletion layer.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2008년도 하계학술대회 논문집
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• pp.379-381
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• 2008

Generally additional leakage inductance and two clamp diodes are adopted into the conventional phase shift full bridge (PSFB) converter for reducing the voltage stress of secondary rectifier diodes and extending the range of zero voltage switching (ZVS) operation. However, since additional leakage inductance carries the ac current similar to the primary one, the core and copper loss oriented from additional leakage inductance can be high enough to decrease the whole efficiency of DC/DC converter. Therefore, in this paper, a new ZVS phase shift full bridge converter with separated primary winding (SPW) is proposed. Proposed converter makes the transformer and additional leakage inductor with one ferrite core. Using this method, leakage inductance is controlled by the winding ratio of separated primary winding. Moreover, by manufacturing the both magnetic components with one core, size and core loss can be reduced and it turns out the improvement of efficiency and power density of DC/DC converter. The operational principle of proposed converter is analyzed and verified by the 1.2kW prototype.

• 한국건축시공학회지
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• 제19권1호
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• pp.19-29
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• 2019

본 연구에서는 공동주택 지하주차장 상부슬래브 등 주로 수평부에 적용되는 아스팔트 매스틱 도막재의 누유하자 원인을 바탕으로 제품의 누유안정성 확보 여부를 평가할 수 있는 평가방법을 개발 및 제시하였다. 본 연구에서 제시한 평가방법의 신뢰성을 검증하기 위하여 실제 현장에서 누유 발생 이력이 있는 3개 제품을 대상으로 누유안정성 평가를 진행하였으며, 진행 결과, 실제 발생하는 누유하자의 재연이 가능한 것으로 확인되었다. 재연성에 대한 정량적 검증을 위해 평가 중에 발생한 누유 시료를 채취하여 회분(Filler)함량을 측정한 결과, 정상시료 대비 최대 약 64%가 저하된 것을 확인하였는데, 이는 선행연구에서 규명한 누유원인과 일치하는 결과로 확인하여, 평가방법의 신뢰성이 검증되었다 할 수 있다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제9권4호
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• pp.240-248
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• 2009

Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus many studies have introduced low power methodologies. However, there are few studies to minimize implementation cost in the mixed use of the methodologies to the best of our knowledge. In this paper, we introduce industrial applications of low power design methodologies for the decrease of leakage current. We focus on the design cost reduction of power gating and reverse body bias when used together. Also, we present voltage scale as an alternative to reverse body bias. To sustain gate leakage current, we discuss the adoption of high-$\kappa$ metal gate, which cuts gate leakage current by a factor of 10 in 32 nm CMOS technology. A 45 nm mobile SoC is shown as the case study of the mixed use of low power methodologies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권4호
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• pp.263-268
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• 2004

In this paper, we motivate the post-mask performance enhancement technique combined with the Multi-Threshold Voltage CMOS (MTCMOS) leakage current suppression technology, and integrate the new design issues related to the MTCMOS technology into the ASIC design methodology. The issues include short-circuit current and sneak leakage current prevention. Towards validating the proposed techniques, a Personal Digital Assistant (PDA) processor has been implemented using the methodology, and a 0.18um process. The fabricated PDA processor operates at 333MHz which has been improved about 23% at no additional cost of redesign and masks, and consumes about 2uW of standby mode leakage power which could have been three orders of magnitude larger if the MTCMOS technology was not applied.

• Journal of Electrical Engineering and Technology
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• 제8권6호
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• pp.1503-1511
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• 2013

This paper deals with the analysis of leakage current characteristics of silicone rubber insulator in order to develop a new condition monitoring tool to identify the flashover of outdoor insulators. In this work, laboratory based pollution performance tests are carried out on silicone rubber insulator under ac voltage at different pollution levels and relative humidity conditions with sodium chloride (NaCl) as a contaminant. Min-Norm spectral analysis is adopted to calculate the higher order harmonics and Signal Noise Ratio (SNR). Choi-Williams Distribution (CWD) function is employed to understand the time frequency characteristics of the leakage current signal. Reported results on silicone rubber insulators show that the flashover development process of outdoor polymer insulators could be identified from the higher order harmonics and signal noise ratio values of leakage current signals.

• 한국IT서비스학회지
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• 제19권2호
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• pp.83-92
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• 2020

The current technology drain at small and medium-sized enterprises in Korea is very serious. According to the National Intelligence Service's survey data, 69 percent of technology leaks are made through employees of small and medium-sized enterprises. A document security system was introduced to compensate for the problem. However, small and medium-sized enterprises are not doing well due to their poor environment. Therefore, it proposes a document security system suitable for small businesses by developing a location information machine learning system that automatically creates a document security Green Zone through learning, and an ECM-based electronic document leakage prevention system that manages generated Green Zone information by reflecting it into the document authority system. And step by step, propose a universal solution through cloud services..

• 융합보안논문지
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• 제15권7호
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• pp.39-45
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• 2015

최근 기업이 보유한 산업기밀은 영업비밀보호법, 산업기술유출방지법 등 다양한 산업보안 관련 법률에 의해 보호 받고 있다. 그러나 그러한 보호에도 불구하고 산업기밀의 침해 및 유출사고는 해마다 증가하고 있다. 한국산업기술보호협회의 조사에 따르면 산업기밀 유출 예상 피해액은 연평균 "50조 원"으로 추정되며 이는 중소기업 4,700여 개의 연 매출액과 맞먹는 금액이다. 이처럼 산업기밀 유출은 국가와 기업의 경쟁력은 물론이고 경제적으로도 심각한 피해를 초래한다. 하지만 산업기밀 유출범죄에 대한 투자와 노력은 피해규모에 비해 한 없이 부족한 수준이며 일부 대기업을 제외한 대부분의 기업들이 산업기밀 유출보안을 위한 별도의 조직, 인력, 예산이 없어 산업기밀 유출에 대한 대응체계가 부족한 것이 현실이다. 본 논문은 국내외 산업기밀 유출범죄 분석을 통하여 산업기밀 유출에 따른 피해실태를 파악하고 발생원인, 유출경로 등 다양한 분류체계를 통하여 산업기밀 유출범죄에 대한 전반적인 흐름을 파악하여 관련 연구에 대한 기초자료가 될 것으로 기대한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.343-346
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• 2004

This paper proposes a leakage-suppressed SRAM with dynamic power saying scheme for the future leakage-dominant sub-70-nm technology. By dynamically controlling the common source-line voltage ($V_{SL}$) of sleep cells, the sub-threshold leakage through these sleep cells can be reduced to be 1/10-1/100 due to the reverse body-bias effect, dram-induced barrier lowering (DIBL) and negative $V_{GS}$ effects. Moreover, the bit-ling leakage which mar introduce a fault during the read operation can be completely eliminated in this new SRAM. The dynamic $V_{SL}$ control can also reduce the bit-line swing during the write so that the dynamic power in write can be reduced. This new SRAM was fabricated in 0.35-${\mu}m$ CMOS process and more than $30\%$ of dynamic power saying is experimentally verified in the measurement. The leakage suppression scheme is expected to be able to reduce more than $90\%$ of total SRAM power in the future leakage-dominant 70-nm process.