• KIEE International Transactions on Electrophysics and Applications
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• v.4C no.6
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• pp.300-305
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• 2004

In this paper, new design equations based on the pole-zero analysis for multi-layered interdigital stripline linear group delay bandpass filter with tap input ports are presented. As a design example, a four-pole group delay filter with center frequency of 2.14GHz, bandwidth of 160MHz, and group delay variation of $\pm$0.1nS for LTCC technology or multilayered PCB technology is designed. In the design process, it is not necessary to simulate the entire structure, as the simulation of half structures is sufficient. Good results can be attained after the optimizing process was performed three times using the proposed equations and a commercial EM simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.65-73
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• 2007

This paper introduces design-for-test (DFT) techniques for low-cost system-on-chip (SoC) test. We present a Scan-Test method that controls IEEE 1500 wrapper thorough IEEE 1149.1 SoC TAP (Test Access Port) and design an at-speed test clock generator for delay fault test. Test cost can be reduced by using small number of test interface pins and on-chip test clock generator because we can use low-price automated test equipments (ATE). Experimental results evaluate the efficiency of the proposed method and show that the delay fault test of different cores running at different clocks test can be simultaneously achieved.

• International Journal of Computer Science & Network Security
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• v.23 no.6
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• pp.27-34
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• 2023

This paper proposed an Inter-Carrier-Interference (ICI) Canceling Orthogonal Frequency Division Multiplexing (OFDM) receiver for 5G mobile system to support 500 km/h linear motor high speed terrestrial transportation service. A receiver in such high-speed train sees the transmission channel which is composed of multiple Doppler-shifted propagation paths. Then, a loss of sub-carrier orthogonality due to Doppler-spread channels causes ICI. The ICI Canceler is realized by the following three steps. First, using the Demodulation Reference Symbol (DMRS) pilot signals, it analyzes three parameters such as attenuation, relative delay, and Doppler-shift of each multi-path component. Secondly, based on the sets of three parameters, Channel Transfer Function (CTF) of sender sub-carrier number 𝒏 to receiver sub-carrier number 𝒍 is generated. In case of 𝒏≠𝒍, the CTF corresponds to ICI factor. Thirdly, since ICI factor is obtained, by applying ICI reverse operation by Multi-Tap Equalizer, ICI canceling can be realized. ICI canceling performance has been simulated assuming severe channel condition such as 500 km/h, 2 path reverse Doppler Shift for QPSK, 16QAM, 64QAM and 256QAM modulations. In particular, for modulation schemes below 16QAM, we confirmed that the difference between BER in a 2 path reverse Doppler shift environment and stationary environment at a moving speed of 500 km/h was very small when the number of taps in the multi-tap equalizer was set to 31 taps or more. We also confirmed that the BER performance in high-speed mobile communications for multi-level modulation schemes above 64QAM is dramatically improved by the use of a multi-tap equalizer.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.10a
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• pp.565-568
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• 2008

In this paper, we present bit error rate(BER) performance of an adaptive decision feedback equalizer(DFE) with experimental data. The experiment was performed at the shore of Geoje in November 2007. The BER performance of the adaptive DFE whose tap weight is updated by RLS is described with change of feedforward tap number, feedback tap number, traning seqence length and delay, which shows that the uncoded average BER is $4{\times}10^{-2}\;and\;1.5{\times}10^{-2}$ with transmission range 9.7km and 4km, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.1 s.343
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• pp.37-44
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• 2006

This paper proposes an interconnect delay fault test (IDFT) solution on boards and SoCs based on IEEE 1149.1 and IEEE P1500. A new IDFT system clock rising edge generator which forces output boundary scan cells to update test data at the rising edge of system clock and input boundary scan cells to capture the test data at the next rising edge of the system clock is introduced. Using this proposed circuit, IDFT for interconnects synchronized to different system clocks in frequency can be achieved efficiently. Moreover, the proposed IDFT technique does not require any modification of the boundary scan cells or the standard TAP controller is simple in terms of test procedure and is small in terms of area overhead.

• Journal of Positioning, Navigation, and Timing
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• v.3 no.2
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• pp.37-44
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• 2014

The most effective method to overcome GPS jamming problem is to use an adaptive array antenna which has the capability of beamforming or nulling to a certain direction. In this paper, Space Time Adaptive Processing (STAP) beamforming algorithm of four elements array antenna will be designed and the anti-jamming performance will be analyzed. According to the analysis, the signal to noise ratio (SNR) and anti-jamming performance can be enhanced by beamforming algorithm. Also, the time tap effect of STAP algorithm will be analyzed theoretically and verified with array antenna modeling and simulation. Specially, the cautious selection of reference time tap in STAP can prevent the degradation of position accuracy performance.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.376-379
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• 1999

The wavelet transform chip is implemented with Daubechies' 4 tap filter. It works at 20MHz in Field Programmable Gate array (FPGA) implementation of Quadrature Mirror Filter(QMF) Lattice Structure. In this paper, the structure contains taro-channel quadrature mirror filter, data format converter(DFC), delay control unit(DCU), and three 20$\times$8 bits real multiplier. The structures for the DFC and DCU need to he regular and scalable, require minimum number of regular, and thereby lead to an efficient and scalable architecture for the Discrete Wavelet Transform(DWT). These results present the possibility that it can be used in Digital Signal Processing(DSP) application faster than Fourier transform at small area with lour cost.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.353-357
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• 2006

One-sided and two-sided ATF for GNSS receiver are deigned, implemented and evaluated in this paper. The difference f filter characteristics such as the location of zeros and the frequency response is reviewed and examined with experiments. NLMS adaptation algorithm is adopted for updating the weighting coefficients of the 12-tap FIR filter. he performance of ATF is evaluated using real signals consisting of the signals from GPS simulator and the signal generator. The output of ATF is fed into the SDR to evaluate SNR and the position accuracy. The complexity of implementation is also compared and the effects of the time delay and the phase delay are examined. The experimental results show that one-sided and two-sided ATF give similar performance against single tone CWI.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.2
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• pp.1355-1363
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• 2015

In order to maintain customer voltage within allowable limit($220{\pm}13V$), tap operation of SVR(step voltage regulator) installed in primary feeder could be carried out according to the scheduled delay time(30 sec) of SVR. However, the compensation of BESS(battery energy storage system) is being required because the customer voltages during the delay time of SVR have a difficultly to maintain within allowable limit when PV system is interconnected with primary feeder. Therefore, this paper presents modeling of SVR to regulate voltage with the LDC(line drop compensation) method and modeling of BESS to control active and reactive power bi-directionally. And also, this paper proposes the coordination control modeling between BESS and SVR in order to overcome voltage problems in distribution system. From the simulation results based on the modeling with the PSCAD/EMTDC, it is confirmed that proposed modeling is practical tool for voltage regulation analysis in distribution system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.241-250
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• 1996

In this work, an improved architecture of two-dimensional digital filter(2D DF) is suggested, and then the filter is simulated by C, VHDL language and related layouts are designed by Berkeley CAD tools. The 2D DF consists of one-dimensional digital filters and delay lines. For one-dimensional digital filter(1D DF) case, once filter coefficients are represented by canonical signed digit formats, multiplications are exected by hardwired-shifting methods. The related bit numbers are handled to prevent picture quality degradation and pipelined adder architectures are adopted in each tap and output stage to speed up the filter. For delay line case, line-sharing DRAM is adopted to improve power dissipation and speed. The filter layout is designed by semi/full custom methods considering regularity and speed improvement, and normal operation is confirmed by simulation.